EP0525986B1 - Appareil à copie rapide entre des tampons de trame dans un système d'affichage à double mémoire-tampon - Google Patents

Appareil à copie rapide entre des tampons de trame dans un système d'affichage à double mémoire-tampon Download PDF

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Publication number
EP0525986B1
EP0525986B1 EP92305993A EP92305993A EP0525986B1 EP 0525986 B1 EP0525986 B1 EP 0525986B1 EP 92305993 A EP92305993 A EP 92305993A EP 92305993 A EP92305993 A EP 92305993A EP 0525986 B1 EP0525986 B1 EP 0525986B1
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Prior art keywords
frame buffer
central processing
processing unit
data signal
address
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EP92305993A
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German (de)
English (en)
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EP0525986A3 (en
EP0525986A2 (fr
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Curtis Priem
Bruce Mcintyre
Chris Malachowsky
Guy Moffat
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Sun Microsystems Inc
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Sun Microsystems Inc
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster

Definitions

  • This invention relates to computer output display apparatus and, more particularly, to methods and apparatus for eliminating frame tearing from a computer output display through the use of inexpensive double buffering.
  • a typical computer system generates data which is displayed on an output display.
  • This output display is typically a cathode ray tube which produces a number of full screen images one after another so rapidly that to the eye of the viewer the screen will appear to display constant motion when a program being displayed is capable of producing such motion.
  • data is written into a frame buffer.
  • the frame buffer stores information about each position on the display which can be illuminated (each pixel) to produce the full screen image.
  • a display may be capable of displaying pixels in approximately one thousand horizontal rows each having approximately one thousand pixels. All of this information in each frame is written to the frame buffer before it is scanned to the display.
  • the frame When data describing an entire picture exists in the frame buffer, the frame may be transferred to the display. Typically, data is transferred from the frame buffer to the display pixel by pixel and line by line beginning at the upper left hand corner of the display and proceeding horizontally from left to right line by line downwardly to the lower right hand corner of the display. In order for the picture to appear continuous on the output display, the successive frames in the frame buffer must be constantly scanned to the output display at a rate of thirty frames per second or more.
  • VRAM video random access memory
  • Double buffering uses two complete frame buffers each of which may store one entire frame. Data is written to one frame buffer and scanned to the display from the other. In its simplest form, this is accomplished using a pair of VRAM frame buffers and multiplexing the data in one or the other to the display. In this form, data is never written to the frame buffer during the time its data is being scanned to the display. Once a frame has been completely written, it may in turn be scanned to the display and all further data written to the other frame buffer. Since data is never written to a frame buffer while its contents are being scanned to the display, frame tearing cannot occur.
  • This simple form of double buffering is somewhat expensive because it uses two entire VRAM frame buffers and includes control signal generating circuitry and a multiplexor for switching between the two frame buffers.
  • One of the primary aims of computer designers is to allow a number of individual programs to run on a computer and be displayed simultaneously on an output display of that computer.
  • a number of individual programs are displayed on a computer output display, each individual program appears in a window, typically a rectangular area of the screen which may be moved about, enlarged and reduced in size, and otherwise manipulated. If a number of programs can be run and displayed in a number of windows simultaneously, the work being accomplished using the computer may be accelerated.
  • information being written to the individual windows by the different individual programs will be written at different rates.
  • the information being directed to a window displaying real time video changes very rapidly while the information typed from the keyboard to a word processor program being displayed in another window changes much more slowly. Consequently, the rate at which frames are changed varies from program to program.
  • the simplest form of double buffering described above is very useful when a single program is being run on the output display.
  • this form of double buffering is insufficient.
  • the simple form of double buffering requires that the entire contents of each frame buffer be scanned to the display. If data is being written to a number of windows at asynchronous rates, then the timing at which writing occurs differs from window to window; and it is very difficult to adjust the timing of the writing so that writing does not occur to a frame buffer being scanned to the display.
  • an advanced form of double buffering has been used which adds another buffer called a window identification (ID) plane.
  • ID window identification
  • the window identification plane provides a storage position for each pixel displayed on the output display. Stored in these positions of the window ID plane are identifications of the window to which each pixel of data is related. Use of this plane allow pixels from any buffer to be selected for display at any time. Thus, the window ID plane may be used to scan to the display data from any window to which data is not being written at the time of the scan. Thus, this form of double buffering allows frame tearing to be eliminated where multiple active windows appear simultaneously on the output display.
  • This second form of double buffering is quite expensive because it not only uses two entire VRAM frame buffers and circuitry for controlling and multiplexing from the two frame buffers to the display, it also adds an ID plane containing memory for each pixel of the display and circuitry for selecting pixels to be displayed based on the windows in which they appear.
  • This form of double buffering is much less expensive than the other forms because a less expensive DRAM replaces one of the VRAM frame buffers and the control circuitry for multiplexing is eliminated.
  • This arrangement is also useful because it works well with software conforming to the X11 standard (X Windows) which does not expect to see more than a single frame buffer and stores information to be transferred to the frame buffer in a section of main memory. To this software, the DRAM frame buffer appears to be a portion of main memory.
  • the arrangement also offers the advantage that individual windows may be transferred from the invisible DRAM frame buffer to the VRAM frame buffer since the central processing unit may selectively control the areas to be transferred.
  • an output display system and a method of accomplishing fast transfer of a data signal comprising a first frame buffer; a second frame buffer; means for transferring data from the second frame buffer to an output display device; means for controlling the transfer of data to each of the frame buffers, this last-mentioned means including means for writing new data only to the first frame buffer, and means for both reading data from the first frame buffer and writing the data read to the second frame buffer during the same operation.
  • the UK Patent Application 2215959A discloses a graphic display system utilizing a high speed copy operation.
  • the graphics display system contains, in part, a graphics processor, an off-screen memory, and a screen refresh memory.
  • the graphics processor, screen refresh memory and off-screen memory are coupled by a data bus.
  • the data bus is utilized to transfer pixel data for the high speed copy operation.
  • the graphics display system utilizes an address generator for each memory.
  • the off-screen memory contains XY offset logic.
  • An address bus couples the graphics processor, the screen refresh memory address generator, and the XY offset logic.
  • the XY offset logic contains a X offset register, a Y offset register, a multiplexor and an adder.
  • the graphics processor generates a single two dimensional address for the fast copy operation.
  • the single two dimensional address identifies the memory location on the screen refresh memory.
  • the graphics processor loads a X offset value and a Y offset value into the Y offset register and the Y offset register, respectively.
  • a two dimensional address is generated by adding the X offset value to the X address, and by adding the Y offset value to the Y address. Consequently, to perform a high speed copy operation between the off-screen memory and the screen refresh memory, the graphics processor provides an address for the screen refresh memory address generator and the XY offset logic.
  • the XY offset logic then adds the offset values stored in the XY offset registers.
  • the address is then provided to the off-screen memory address generator.
  • Both address generators generate row and column addresses by holding both the x and y addresses for each memory.
  • the fast copy operation permits transfer of pixel data from the screen refresh memory to the off-screen memory and from the off-screen memory to the screen refresh memory through use of read and write enable signals.
  • Figure 1 is a block diagram illustrating a prior art arrangement for reducing the cost of double buffering arrangements.
  • Figure 2 is a block diagram of an arrangement in accordance with the present invention for providing double buffering.
  • the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind.
  • the present invention relates to apparatus and to method steps for operating a computer in processing electrical or other (e.g. mechanical, chemical) physical signals to generate other desired physical signals.
  • circuit 10 constructed in accordance with the prior art.
  • the circuit 10 includes only the rudiments of the circuitry required to provide data to an output display terminal used in a typical computer system. Other portions necessary for providing the operations of a computer are well known to those skilled in the art and are not shown in the figure. Illustrated are a central processing unit 12 which may control the operation of the entire computer system and which represents in Figure 1 circuitry for providing data to be display on an output display 14. In order to accomplish the transfer of the data from the central processing unit 12 to the output display 14, first and second frame buffers 16 and 17 are utilized.
  • double buffering data is written from the central processing unit 12 to one frame buffer and scanned to the display 14 from the other. In its simplest form, this is accomplished using a pair of VRAM frame buffers and multiplexing the entire frame of data in one of the frame buffers 16 or 17 to the display by means of a multiplexor 19. The data transferred by the multiplexor 19 is converted from digital to analog form by a digital-to-analog converter 20 and scanned to the display. In this form of double buffering, data is never written to a frame buffer 16 or 17 during the time data is being scanned to the display from that frame buffer.
  • the data in that frame buffer may in turn be scanned to the display; and new data may be written to the other frame buffer. Since data is never written to a frame buffer while its contents are being scanned to the display, frame tearing cannot occur.
  • one prior art arrangement has replaced the VRAM used in the frame buffer 16 with DRAM. Since DRAM is single ported, the frame buffer 16 does not provide an output which may be scanned directly to the display 14. Consequently, the lines from the frame buffer 16 to the multiplexor 19 (which are dotted in the figure) are eliminated. Since no output is transferred from the frame buffer 16 to the multiplexor 19, the multiplexor 19 (again shown in dotted outline) is also eliminated. With no multiplexor, the control circuitry for selecting one or the other of the frame buffers 16 or 17 to scan to the display 14 is also unnecessary and is eliminated. This substantially reduces the cost of the system.
  • All new data is written by the central processing unit 12 to the frame buffer 16. All data is scanned to the display 14 from the frame buffer 17. Once a frame stored in frame buffer 16 has been changed, the frame is transferred to the frame buffer 17. To accomplish this transfer, a control circuit 23 within the central processing unit 12 selects a portion of the frame buffer 16 to be read, typically thirty-two bits or some amount usually equivalent to the width of the bus. This data is read and latched into the central processing unit 12. This read typically requires three clock periods for row addressing and four clock periods for column addressing by the control circuit 23. The central processing unit 12 then writes the information read from the frame buffer 16 to the frame buffer 17. This again typically requires three clock cycles for row addressing by the control circuitry 23 in frame buffer 17 and three clock cycles for column addressing in that frame buffer.
  • the additional clock period for column addressing in reading frame buffer 16 during the read operation is actually necessary in order to provide a dead cycle on the bus between the reading by the central processing unit 12 of the frame buffer 16 and the following write cycle to the frame buffer 17 so that two devices are not accessing the bus simultaneously.
  • a total of thirteen or more clock cycles are required to transfer a given amount of information from the frame buffer 16 to the frame buffer 17 in this arrangement.
  • This transfer is repeated a sufficient number of times to transfer the desired amount of data (which may be as large as an entire frame) from the frame buffer 16 to the frame buffer 17.
  • this is a relatively slow process and, when copying entire frames, allows only approximately twenty frames to be transferred per second.
  • a typical display may be receiving information from the frame buffer 17 at a rate of seventy-six frames per second. The scan proceeds at approximately three times the rate of the write to the frame buffer 17.
  • this less expensive arrangement allows the scan to the display to catch up with the writing of data into the frame buffer 17 from the frame buffer 16 so that frame tearing may occur.
  • the arrangement 25 includes a central processing unit 27, a first frame buffer 28 which may be constructed of VRAM, a second frame buffer 29 which may be constructed of DRAM, a digital-to-analog converter 31, and an output display 33.
  • the arrangement 25 functions in the same general manner as does the least expensive arrangement of Figure 1. That is, all new data is written by the central processing unit 27 to the DRAM frame buffer 29. All data is scanned to the display 33 from the VRAM frame buffer 28. Once new data has been written to a frame stored in frame buffer 29, the frame is transferred to the frame buffer 28. To accomplish this transfer, the central processing unit 27 reads a selected portion of the frame buffer 29, typically thirty-two bits, and writes that data to the frame buffer 28. This process is accomplished over and over until the desired amount of data has been transferred.
  • the arrangement of the present invention transfers the data approximately four times as fast.
  • approximately eighty frames per second may be written to the frame buffer 28 from the frame buffer 29; and tearing of frames scanned to the display may be eliminated.
  • the arrangement 25 includes within the central processing unit 27 (or other device controlling the rendering into and reading from the frame buffers 28 and 29) a pair of individual control circuits 34 and 35.
  • the first of these circuits 34 controls the accessing of the frame buffer 29, and the second circuit 35 controls the accessing of the frame buffer 28.
  • both frame buffers 28 and 29 may be accessed simultaneously. Data is still written only to the frame buffer 29 by the central processing unit when rendering.
  • control circuit 34 selects the appropriate row and column addresses in the frame buffer 29, and the control circuit 35 selects the same row and column addresses in the frame buffer 28. Then the control circuit 34 reads the accessed data in the frame buffer 29 and places it on the bus where the information is written to the same accessed addresses in the frame buffer 28. The data is not latched into the central processing unit 27; and, consequently, no dead cycle is needed for bus turn around so that two devices are not attempting to access that bus simultaneously.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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Claims (18)

  1. Procédé pour exécuter le transfert rapide d'un signal de données dans un système d'affichage de sortie d'ordinateur, comprenant une unité centrale de traitement (27), une mémoire tampon de trame DRAM (29), une mémoire tampon de trame VRAM (28), un bus, et un dispositif d'affichage de sortie (33), selon lequel ledit signal de données est transféré depuis ladite mémoire tampon de trame DRAM à ladite mémoire tampon de trame VRAM pour son affichage dans ledit dispositif d'affichage de sortie, ledit procédé comprenant les étapes consistant en ce que :
    • ladite unité centrale de traitement applique une première adresse de ligne et une première adresse de colonne à ladite mémoire tampon de trame VRAM tout en appliquant simultanément et de façon indépendante une seconde adresse de ligne et une seconde adresse de colonne à ladite mémoire tampon de trame VRAM ;
    • ladite unité centrale de traitement déclenche le transfert d'un signal de données mémorisé à ladite première adresse de ligne et à ladite première adresse de colonne dans ladite mémoire tampon de trame DRAM audit bus ;
    • ladite unité centrale de traitement commande le transfert dudit signal de donnée depuis ledit bus à ladite seconde adresse de ligne et à ladite seconde adresse de colonne dans ladite mémoire tampon de trame VRAM ;
    • ledit signal de données étant disponible de manière à être exploré dans ladite mémoire tampon de trame VRAM avec transfert audit dispositif d'affichage de sortie pour l'affichage.
  2. Procédé pour exécuter le transfert rapide d'un signal de données selon la revendication 1, selon lequel ledit signal de données est transféré depuis ledit bus à ladite seconde adresse de ligne et à ladite seconde adresse de colonne dans ladite mémoire tampon de trame VRAM, sans verrouillage dudit signal de données dans ladite unité centrale de traitement.
  3. Procédé pour exécuter le transfert rapide d'un signal de données dans un système d'affichage de sortie d'ordinateur, comprenant une unité centrale de traitement (27), une première mémoire tampon de trame (29), un seconde mémoire tampon de trame (28), un bus, et un dispositif d'affichage de sortie (33), selon lequel ledit signal de données est transféré depuis ladite mémoire tampon de trame à ladite seconde mémoire tampon de trame, ledit procédé comprenant les étapes consistant en ce que :
    • ladite unité centrale de traitement applique une première adresse de ligne et une première adresse de colonne à ladite seconde mémoire tampon de trame tout en appliquant simultanément et de façon indépendante une seconde adresse de ligne et une seconde adresse de colonne à ladite seconde mémoire tampon de trame ;
    • ladite unité centrale de traitement déclenche le transfert d'un signal de données mémorisé à ladite première adresse de ligne et à ladite première adresse de colonne dans ladite première mémoire tampon de trame depuis ladite première mémoire tampon de trame audit bus ;
    • ladite unité centrale de traitement commande le transfert dudit signal de données depuis ledit bus à ladite seconde adresse de ligne et à ladite seconde adresse de colonne dans ladite seconde mémoire tampon de trame ;
    • ledit signal de données étant disponible de manière à être exploré dans la seconde mémoire tampon de trame avec transfert audit dispositif d'affichage de sortie pour l'affichage.
  4. Procédé pour exécuter le transfert rapide d'un signal de données selon la revendication 3, dans lequel ladite première mémoire tampon de trame (29) comprend une mémoire DRAM comportant un seul port.
  5. Procédé pour exécuter le transfert rapide d'un signal de données selon la revendication 4, dans lequel ladite seconde mémoire tampon de trame (28) comprend une mémoire VRAM comportant au moins deux ports.
  6. Procédé pour exécuter le transfert rapide d'un signal de données selon la revendication 3, selon lequel ledit signal de données est transféré depuis ledit bus à ladite seconde adresse de ligne et à ladite seconde adresse de colonne dans ladite seconde mémoire tampon de trame, sans verrouillage dudit signal de données dans ladite unité centrale de traitement.
  7. Procédé pour exécuter le transfert rapide d'un signal de données selon la revendication 3, selon lequel ladite première adresse de ligne et ladite seconde adresse de ligne sont sélectionnées par ladite unité centrale de traitement sur la base de la ligne, éventuellement présente, actuellement explorée de manière à être explorée avec transfert de ladite seconde mémoire tampon de trame audit dispositif d'affichage de sortie.
  8. Procédé pour exécuter le transfert rapide d'un signal de données selon la revendication 3, selon lequel ladite première adresse de ligne est une adresse équivalente de ladite seconde adresse de ligne, et ladite première adresse de colonne est une adresse équivalente de ladite seconde adresse de colonne.
  9. Système d'affichage de sortie d'ordinateur comprenant :
    • une unité centrale de traitement (27) ;
    • une première mémoire tampon de trame (29) couplée à ladite unité centrale de traitement par l'intermédiaire d'un premier bus de transmission d'adresses ;
    • une seconde mémoire tampon de trame (28) couplée à ladite unité centrale de traitement par l'intermédiaire d'un second bus de transmission d'adresses ;
    • un bus de transmission de données couplé à ladite unité centrale de traitement, à ladite première mémoire tampon de trame et à ladite seconde mémoire tampon de trame ;
    • un convertisseur numérique/analogique (31) couplé à ladite seconde mémoire tampon de trame (28) ;
    • un dispositif d'affichage de sortie (33) couplé audit convertisseur numérique/analogique (31) ;
    • ladite unité centrale de traitement (27) comprenant des moyens de transfert rapide pour sélectionner une première adresse de ligne et une première adresse de colonne dans ladite première mémoire tampon de trame par l'intermédiaire dudit premier bus de transmission d'adresses, avec sélection simultanée d'une seconde adresse de ligne et d'une seconde adresse de colonne dans ladite seconde mémoire tampon de trame par l'intermédiaire dudit second bus de transmission d'adresses, puis provoquer le transfert d'un signal de données mémorisé à ladite première adresse de ligne et à ladite première adresse de colonne dans ladite première mémoire tampon de trame audit bus de transmission de données et depuis ledit bus de transmission de données à ladite seconde adresse de ligne et à ladite seconde adresse de colonne dans ladite seconde mémoire tampon de trame.
  10. Système d'affichage de sortie d'ordinateur selon la revendication 9, dans lequel lesdits moyens de transfert rapide comprennent :
    • un premier circuit de commande (34) pour commander des accès de lecture de ladite unité centrale de traitement (27) à ladite première mémoire tampon de trame (29); et
    • un second circuit de commande (35) pour commander des accès d'écriture de ladite unité centrale de traitement (27) à ladite seconde mémoire tampon de trame (28).
  11. Système d'affichage de sortie d'ordinateur selon la revendication 10, dans lequel ladite première mémoire tampon de trame (29) comprend une mémoire DRAM comprenant un premier port, de telle sorte que ledit premier port est couplé à ladite unité centrale de traitement.
  12. Système d'affichage de sortie d'ordinateur selon la revendication 11, dans lequel ladite seconde mémoire tampon de trame (28) comprend une mémoire VRAM comportant un second port et un troisième port, de sorte que ledit second port est couplé à ladite unité centrale de traitement et ledit troisième port est couplé audit convertisseur numérique/analogique.
  13. Système d'affichage de sortie d'ordinateur selon la revendication 9, dans lequel lesdits moyens de transfert rapide comprennent des moyens pour sélectionner ladite première adresse de ligne et ladite seconde adresse de ligne sur la base de la ligne, éventuellement présente, qui est actuellement explorée avec transfert de ladite seconde mémoire tampon de trame audit dispositif d'affichage de sortie.
  14. Système d'affichage de sortie d'ordinateur selon la revendication 9, dans lequel lesdits moyens de transfert rapide comprennent des moyens pour transférer ledit signal de données depuis ledit bus à ladite seconde adresse de ligne et à ladite seconde adresse de colonne dans ladite seconde mémoire tampon de trame, sans verrouillage dudit signal de données dans ladite unité centrale de traitement.
  15. Système d'affichage de sortie d'ordinateur selon la revendication 14, dans lequel lesdits moyens de transfert rapide comprennent :
    • un premier circuit de commande (34) pour commander des accès de lecture de ladite unité centrale de traitement (27) à ladite première mémoire tampon de trame (29) ; et
    • un second circuit de commande (35) pour commander des accès d'écriture de ladite unité centrale de traitement (27) à ladite seconde mémoire tampon de trame (28).
  16. Système d'affichage de sortie d'ordinateur selon la revendication 15, dans lequel ladite première mémoire tampon de trame (29) comprend une mémoire DRAM comportant un premier port, de telle sorte que ledit premier port est couplé à ladite unité centrale de traitement.
  17. Système d'affichage de sortie d'ordinateur selon la revendication 16, dans lequel ladite seconde mémoire tampon de trame (28) comprend une mémoire VRAM comportant un second port et un troisième port, de telle sorte que ledit second port est couplé à ladite unité centrale de traitement et ledit troisième port est couplé audit convertisseur numérique/analogique.
  18. Système d'affichage de sortie d'ordinateur selon la revendication 17, dans lequel lesdits moyens de transfert rapide comprennent en outre des moyens pour sélectionner ladite première adresse de ligne et ladite seconde adresse de ligne sur la base de la ligne, éventuellement présente, qui est actuellement explorée avec transfert de ladite seconde mémoire tampon de trame audit dispositif d'affichage de sortie.
EP92305993A 1991-07-26 1992-06-29 Appareil à copie rapide entre des tampons de trame dans un système d'affichage à double mémoire-tampon Expired - Lifetime EP0525986B1 (fr)

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US73668691A 1991-07-26 1991-07-26
US736686 1991-07-26

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EP0525986A2 EP0525986A2 (fr) 1993-02-03
EP0525986A3 EP0525986A3 (en) 1993-07-21
EP0525986B1 true EP0525986B1 (fr) 1996-11-13

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EP (1) EP0525986B1 (fr)
JP (1) JPH06214549A (fr)
KR (1) KR100196686B1 (fr)
DE (1) DE69215155T2 (fr)

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JP3611511B2 (ja) 2000-09-27 2005-01-19 三菱電機株式会社 マトリクス型表示装置及び画像データ表示方法並びに携帯情報端末装置
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DE69215155T2 (de) 1997-06-19
EP0525986A3 (en) 1993-07-21
JPH06214549A (ja) 1994-08-05
DE69215155D1 (de) 1996-12-19
KR100196686B1 (ko) 1999-06-15
KR930002926A (ko) 1993-02-23
EP0525986A2 (fr) 1993-02-03

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