Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y40/00—Manufacture or treatment of nanostructures
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/004—Photosensitive materials
  • G03F7/075—Silicon-containing compounds
  • G03F7/0751—Silicon-containing compounds used as adhesion-promoting additives or as means to improve adhesion
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/20—Exposure; Apparatus therefor
  • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
  • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
  • H01J37/3174—Particle-beam lithography, e.g. electron beam lithography

Definitions

• This invention relates in general to a hybrid lithographic process, and more particularly to an intra-level hybrid electron beam/optical photolithography process.
• photol thography techniques are widely used for patterning semiconductor substrates or for patterning thin layers of material overlying semiconductor substrates, PC boards, and the like.
• a layer of photoresist is applied and portions of the photoresist material are exposed, usually through a mask, to cause exposed and unexposed portions to have different dissolu-. tion rates in a photoresist developer.
• one of the exposed or unexposed portions is removed to leave a patterned mask layer on the underlying material.
• the patterned photoresist layer then may be used as an etch mask, ion implant mask, metal lift-off mask, or the like.
• Electron beam exposure is capable of delineating fine pattern geometries, but has the disadvantage that exposure of large areas is very time consuming because the exposure is made with an electron beam of small cross sectional area.
• Resist materials can be classified as either negative or positive resists. With negative resist, the unexposed resist portion is removed during the developing process; with positive resists, the opposite is true and only the unexposed portions remain after developing.
• negative resist the unexposed resist portion is removed during the developing process; with positive resists, the opposite is true and only the unexposed portions remain after developing.
• negative resist the unexposed resist portion is removed during the developing process; with positive resists, the opposite is true and only the unexposed portions remain after developing.
• a pattern such as a gate electrode pattern on a complex MOS IC, in which fine geometries are required but in which only a small proportion of the total surface area is to remain covered
• the use of negative resists and an electron beam exposure process would be advantageous.
• the electron beam could provide the necessary high resolution pattern but only a small portion of the resist layer would have to be exposed.
• Negative electron beam resists suffer from swelling effects, especially for pattern sizes less than about 1 micron. The swelling effect can result in poor replication of the desired pattern. Negative resists are, therefore, generally not acceptable for use in high resolution, fine geometry electron beam processing. To use a positive resist in this application, however, would require the time consuming exposure of a large proportion of the substrate area. The high throughput of a production process, therefore, is seemingly incompatible with the high resolution achievable with electron beam exposure.
• two layers of resist are used. One layer is electron beam exposed in a fine pattern and a first etching step is carried out using this pattern as a mask. Then a second layer of resist is applied and optically exposed to pattern the large substrate areas in a second etching step.
• This inter-layer hybrid process has the obvious disadvantage that a number of extra steps are required.
• the foregoing and other objects and advantages of the invention are achieved through a unique intra-level hybrid process which combines electron beam and optical lithography.
• the substrate upon which a resist pattern is to be formed is prepared by the application of an adhesion promoter which is compatible with both electron beam and optical processing.
• a positive photoresist, sensitive to both electron beam and optical exposure, is applied to the substrate and subsequently exposed.
• the fine geometry portions of the pattern are electron beam exposed and the large areas without fine geometry features are optically exposed.
• the process capable of high throughput, is completed with a resist development step to leave an adherent layer of resist having fine geometry features on the underlying substrate.
• FIGURE illustrates a representative composite mask for patterning an array of fine geometry patterns in accordance with the invention.
• the FIGURE illustrates a portion of a composite mask of the gate level of an MOS integrated circuit.
• the pattern comprises a plurality of gate electrodes 10.
• a layer of electrode material is applied over the surface of the semiconductor substrate. That layer of electrode material must then be patterned and excess electrode material removed to leave only the electrodes. In accordance with an embodiment of the invention, this is accomplished by applying a layer of positive resist over the electrode material.
• the photoresist is exposed by writing with an electron beam around the electrodes. Electron beam writing is capable of producing high resolution patterns and can delineate, for example, a gate electrode pattern having a width of only a fraction of a micrometer.
• the electron beam exposes only the resist around the desired fine geometry electrode 10 and extending outward from the electrode to the edge of the rectangle 12.
• the remaining resist requiring no fine delineation, is then optically exposed using a conventional photo mask that overlays and masks the area already electron beam exposed.
• the necessary photo mask for this step thus need only have a plurality of opaque rectangles which are roughly aligned with the rectangles 12.
• the optical exposure provides for the rapid exposure of the resist material from the remaining area and which in turn provides for the removal of unwanted gate electrode material from the larger area of the semiconductor substrate.
• the resist around the electron beam delineated electrodes 10 is protected from exposure during the optical exposure portion of the process by the opaque rectangles provided on the optical mask.
• the combined exposure, electron beam and optical thus exposes all of the resist material in the single layer of resist except that overlying gate electrodes 10.
• the resist is developed to remove the exposed resist portions.
• the remaining resist, overlying the ultimate gate electrodes, is then used as an etch mask and the unwanted electrode material is etched using wet chemical etching, plasma etching, reactive ion etching, or the like, as needed.
• a resist material In practicing the process in accordance with the invention, a resist material must be used which functions satisfactorily " for both optical and electron beam exposure.
• a number of commercially available resist materials are available which work in this hybrid process.
• One such resist is PC 129 SF, now known as Allied P 2025 made by Allied Chemical Corporation.
• an adhesion promoter is desirable.
• the adhesion promoter must be compatible with a process involving both optical and electron beam exposed portions of the resist.
• the need for an adhesion promoter is especially great when isolated islands of unexposed positive resist material smaller than about 2-3 micrometers in width are formed. It has been found particularly advantageous to use a double adhesion promoter to insure adhesion of very narrow resist areas. In particular, it has been advantageous to use a halogenated silane promoter and then an amino silane promoter with a separate cure step for each promoter.
• a preferred halogenated silane is vinyltrichlorosilane (VTS).
• a preferred amino silane is 1,3-divinyltetramethyldisilazane although materials like hexamethyldisilazane (HMDS) can also be used.
• VTS vinyltrichlorosilane
• HMDS hexamethyldisilazane
• Semiconductor wafers for fabrication of MOS integrated circuits are prepared by steps which include providing a layer of gate insulator on a semiconductor substrate and overlying the insulator layer with a layer of heavily doped polycrystall ine silicon.
• the polycrystall ine silicon material is to be patterned to form gate electrodes of the integrated circuit.
• the substrates are dehydration baked in a 200°C oven purged with dry nitrogen for two hours. After cooling to room temperature, the substrates are immediately flooded with a VTS solution comprising 2.5 cc of vinyltrichloro- silane and 50 cc of xylene. Substrates are then spun at 500 RPM for 1 second and 5000 RPM for 10 seconds. The VTS solution is then thermally cured at 90°C for 10- minutes in a nitrogren purged oven. After cooling to room temperature again, a second adhesion promoter is applied to the substrate by immediately flooding the substrate with undiluted 1 ,3-divinyltetramethyldisil azane , spinning the substrate at 500 RPM for 1 second and then 5000 RPM for 10 seconds. The second adhesion promoter is thermally cured by heating to 90°C in a nitrogen purged oven for 10 minutes.
• a 2:1 diluted resist solution comprising PC 129 SF resist and resist thinner is applied to the adhesion promoted substrates.
• the substrates are spun for 1 second at 500 RPM followed by 20 seconds at 4500 RPM to provide a uniform layer of resist 0.5 micrometer thick.
• the resist coated wafers Prior to exposure the resist coated wafers are pre-baked for 30 minutes in air at 90°C.
• the substrates are first electron beam exposed to del ineate " gate electrode patterns in the resist layer. The resultant width of the pattern is dependent upon electron beam dosage; very narrow gates additionally experience proximity exposure from imaging both sides of the narrow gate. Electron beam doses around the gate electrode patterns are therefore adjusted for the various sized gates being patterned. Gate electrode areas are exposed with doses ranging from about 132 yC/cm 2 for gates of about 0.5 micrometer width to about 139 ⁇ C/cm 2 for 1.0 micrometer width gates.
• the substrates are aligned on a conventional optical photoresist alignment tool.
• the electron beam patterns are covered by an aligned opaque region during an optical exposure of about 15 seconds at 6.0 mW/cm 2 . Additionally, during this exposure, patterns greater than about 3 micrometers in dimension are also optically exposed.
• both the electron beam exposed and the optically exposed images are developed in a single development step using a conventional photoresist developer.
• the substrates are immersion developed in D-900 developer diluted to 2:1 with water at 21°C.
• D-900 is a developer supplied by Polychrome Corporation. The developing is quenched by immersion into pure water followed by spin/spray rinse with water and spin dry.
• the resist patterned substrates are post-baked at 90°C for 30 minutes and then plasma etched in a CC1 based plasma etchant.
• the resist material is stripped from the substrates in oxygen plasma to leave patterned gate electrodes positioned on the gate insulator.
• Integrated circuit substrates comprise semiconductor substrate having a thin gate insulator on one surface.
• a multi -layered structure of gate electrode material comprising a first layer of titanium suicide, a second layer of polyi ide and a third overlying layer of plasma deposited silicon dioxide is provided on the gate insulator.
• Adhesion promoters and resist material are applied as in Example I.
• the multi-layered gate electrode structure is patterned as in Example I with the following exceptions. Because the multi-layered structure has a different atomic number Z than polycrystal1 ine silicon, the electron beam energy must be adjusted to higher values.
• the resist is electron beam exposed with doses ranging from about 148 ⁇ C/cr ⁇ 2 for 0.5 - micrometer gate electrode widths to about 151 ⁇ C/cm 2 for 1.5 micrometer gate widths. Additionally, in etching the multilayer structure, the plasma oxide and polyimide are first reactive ion etched before finally plasma etching the titanium suicide.
• Substrates are prepared and processed as in Example I except that the developer is more dilute to yield a longer, more controllable development time.
• the developer is D-900 diluted with water in a ratio 1:1 and the development time is correspondingly increased to 45 seconds.
• Substrates are prepared and processed as in Example I except for a change in developing.
• the developer is D-900 diluted with water in a ratio 3:2 and the developer is allowed to puddle on the substrates for 20 seconds.
• Puddle development differs from immersion developing in that the substrate sees only a fixed amount of developer, namely that volume of developer held on the wafer by surface tension.
• the developer is flooded onto the wafer and then after 20 seconds the developer is spin/spray rinsed off with clear water followed by a spin dry in air.
• I-IV, patterned gate electrodes are realized having minimum gate dimensions ranging from 0.5 micrometers to 1.5 micrometers.

Landscapes

• Engineering & Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Physics & Mathematics (AREA)
• Nanotechnology (AREA)
• General Physics & Mathematics (AREA)
• Crystallography & Structural Chemistry (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Manufacturing & Machinery (AREA)
• Mathematical Physics (AREA)
• Theoretical Computer Science (AREA)
• Analytical Chemistry (AREA)
• Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
• Photosensitive Polymer And Photoresist Processing (AREA)
• Electron Beam Exposure (AREA)

Applications Claiming Priority (2)

Publications (2)

Family

ID=23429755

Family Applications (1)

Country Status (3)

Families Citing this family (5)

Citations (2)

Family Cites Families (5)

• 1983
  • 1983-03-01 JP JP50148583A patent/JPS59500436A/ja active Pending
  • 1983-03-01 WO PCT/US1983/000273 patent/WO1983003485A1/fr not_active Application Discontinuation
  • 1983-03-01 EP EP19830901447 patent/EP0104235A4/fr not_active Withdrawn

Patent Citations (2)

Non-Patent Citations (7)

Also Published As

Similar Documents

Legal Events