EP0067677B1 - Halbleiteranordnung mit einer Chipreihe-Struktur - Google Patents
Halbleiteranordnung mit einer Chipreihe-Struktur Download PDFInfo
- Publication number
- EP0067677B1 EP0067677B1 EP82303014A EP82303014A EP0067677B1 EP 0067677 B1 EP0067677 B1 EP 0067677B1 EP 82303014 A EP82303014 A EP 82303014A EP 82303014 A EP82303014 A EP 82303014A EP 0067677 B1 EP0067677 B1 EP 0067677B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- chips
- chip
- array
- individual
- connection pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15157—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/166—Material
- H01L2924/16786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/16787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Definitions
- the present invention relates to a semiconductor device, particularly to a chip-array-constructed semiconductor device in which a plurality of semiconductor chips are mounted in a single package.
- IC semiconductor integrated circuit
- semiconductor memory devices such as semiconductor logic devices or semiconductor memory devices
- IC semiconductor integrated circuit
- semiconductor logic devices semiconductor logic devices
- semiconductor memory devices only one semiconductor IC chip is mounted in a package.
- the number of packages on which electric components such as semiconductor IC chips are mounted increases, causing the computer system to be large in scale.
- a plurality of semiconductor IC chips have been mounted in the same package and, accordingly, the packing density of the semiconductor IC chips has increased.
- Such a semiconductor package in which a plurality of semiconductor chips are mounted is called a chip-array-constructed semiconductor device.
- the chips have usually been mounted on a multilayer printed board which forms part of the package.
- a chip-array-constructed semiconductor device comprising a plurality of semiconductor chips having circuit elements thereon and having connection pads, and a mounting of a generally rectangular shape on which the plurality of semiconductor chips are mounted, the mounting carrying a single conducting layer, the semiconductor chips having their connection pads arranged around their periphery with the connection pads that are common to all the chips arranged in corresponding positions along two opposite sides on all the chips, and the single conducting layer being divided into common conducting strips which are connected to the corresponding common connection pads, and into individual conducting strips which are connected to the connection pads that are individual to the individual chips.
- the individual chips have their individual connection pads arranged along one or both ends of the chips, the common conducting strips extend lengthwise along the mounting under the chips and the individual connecting strips extend generally transverse to and at one or both sides of the common conducting strips to external leads located at the ends of the mounting.
- a semiconductor chip 1 has circuit elements (not shown) such as memory cells and the like formed thereon.
- the cross-hatched portions 2-1 to 2-6 indicate common connection pads for receiving common signals such as common power supply voltages, common address signals, and the like while the hatched portion 3 indicates an individual connection pad for receiving an individual signal such as a clock signal, an input/out- put signal, or the like peculiar to this chip.
- Such connection pads are arranged along peripheral portions of the chip 1.
- the pads 2-1 to 2-6 are arranged along the Y-axis while the pads 3 are arranged along the X-axis.
- the connection pads 2-1 through 2-6 and 3 are formed by a single conductive layer such as aluminum (Al) or the like.
- FIG. 2A is a plan view illustrating an embodiment of the package according to the present invention
- Figs. 2B and 2C are cross-sectional views taken along the line B-B' and the line C-C', respectively, of Fig. 2A.
- a package 4 comprises a ceramic base 5, made of alumina or the like, to which a ceramic frame 6 having a metallized layer 7 for sealing thereon is bonded with glass (not shown).
- the ceramic base 5 has recess portions 8 for mounting semiconductor chips thereon.
- a plurality of common conductive strips 9-1 through 9-6 are arranged in parallel to the X-direction and extend to the end face on the longer side of the ceramic base 5.
- a plurality of individual conductive strips 10-1 through 10-4 are arranged on at least one side (in this case, on both sides) of the common conductive strips 9-1 through 9-6 in parallel to the Y-direction and extend to the end surface on the longer side of the ceramic base 5. Note that exposed portions of the conductive strips 9-1 through 9-6 and 10-1 through 10-4 at the edges of the recess portions 8 are called bonding posts.
- Reference numeral 11 indicates a chip base bonded with glass (not shown) to each recess portion 8.
- the chip base 11 is formed from for example, a ceramic plate of alumina, beryllia, or the like.
- Reference numeral 12 indicates an external lead made of Kovar or the like which is bonded by soldering to one of the conductive strips 9-1 through 9-6 and 10-1 through 10-4.
- Figs. 3A, 3B, and 3C which are similar to Figs. 2A, 2B, and 2C, respectively, four semiconductor chips 1-1 through 1-4, which are the same as the chip 1 illustrated in Fig. 1, are mounted on the package as illustrated in Figs. 2A, 2B, and 2C.
- Each of the semiconductor chips 1-1 through 1-4 is fixed by depositing epoxy resin (not shown) on one of the chip bases 11 of the package 4.
- the common conductive strips 9-1 through 9-6 are commonly used for the semiconductor chips 1-1 through 1-4 while the individual conductive strips 10-1, 10-2, 10-3, and 10-4 are peculiar to the semiconductor chips 1-1, 1-2, 1-3, and 1-4, respectively.
- the common connection pads 2-1 through 2-6 of the semiconductor chip 1-1 are electrically connected to the bonding post of one of the common conductive strips 9-1 through 9-6 by bonding wires 13 while the individual connection pads 3 of the semiconductor chip 1-1 are electrically connected to the individual conductive strips 10-1 by bonding wires 14.
- the wires 13 and 14 are made a aluminum, gold, or the like.
- a sealing-completed semiconductor device is illustrated.
- Reference numeral 15 indicates solder material
- 16 is a metallized layerforsealing
- 17 indicates a cap formed from a ceramic plate.
- chip bases 11 made of ceramic material are provided between the semiconductor chips 1-1 through 1-4 and the common conductive strips 9-1 through 9-6; however, such chip bases can be omitted when semiconductor chips having thick insulated layers on the back thereof or SOS chips are used.
- the semiconductor device according to the present invention is advantageous in that the manufacturing cost is low since the semiconductor device, which has a chip-array construction, is formed by using a single conductive layer-constructed package which is manufactured at a low cost. Therefore, the present invention provides semiconductor devices of a high packing density at a low cost, thereby enabling a computer system to be small in size.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP91799/81 | 1981-06-15 | ||
JP56091799A JPS57207356A (en) | 1981-06-15 | 1981-06-15 | Semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0067677A2 EP0067677A2 (de) | 1982-12-22 |
EP0067677A3 EP0067677A3 (en) | 1984-10-03 |
EP0067677B1 true EP0067677B1 (de) | 1987-09-09 |
Family
ID=14036658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP82303014A Expired EP0067677B1 (de) | 1981-06-15 | 1982-06-10 | Halbleiteranordnung mit einer Chipreihe-Struktur |
Country Status (4)
Country | Link |
---|---|
US (1) | US4578697A (de) |
EP (1) | EP0067677B1 (de) |
JP (1) | JPS57207356A (de) |
DE (1) | DE3277268D1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4225154A1 (de) * | 1992-07-30 | 1994-02-03 | Meyerhoff Dieter | Chip-Modul |
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EP0344873B1 (de) * | 1982-06-30 | 1993-12-15 | Fujitsu Limited | Integrierte Halbleiterschaltungsanordnung |
JPS60143641A (ja) * | 1983-12-29 | 1985-07-29 | Konishiroku Photo Ind Co Ltd | 集積回路装置 |
GB8412674D0 (en) * | 1984-05-18 | 1984-06-27 | British Telecomm | Integrated circuit chip carrier |
EP0334397A3 (de) * | 1984-05-18 | 1990-04-11 | BRITISH TELECOMMUNICATIONS public limited company | Schaltungsplatte |
GB2170657B (en) * | 1985-02-05 | 1988-01-27 | Stc Plc | Semiconductor memory device |
US4674007A (en) * | 1985-06-07 | 1987-06-16 | Microscience Corporation | Method and apparatus for facilitating production of electronic circuit boards |
FR2591801B1 (fr) * | 1985-12-17 | 1988-10-14 | Inf Milit Spatiale Aeronaut | Boitier d'encapsulation d'un circuit electronique |
US4751564A (en) * | 1986-05-05 | 1988-06-14 | Itt Corporation | Multiple wafer scale assembly apparatus and fixture for use during the fabrication thereof |
USRE36894E (en) * | 1986-05-27 | 2000-10-03 | Lucent Technologies Inc. | Semiconductor package with high density I/O lead connection |
US4774635A (en) * | 1986-05-27 | 1988-09-27 | American Telephone And Telegraph Company At&T Bell Laboratories | Semiconductor package with high density I/O lead connection |
IT1218104B (it) * | 1986-06-27 | 1990-04-12 | Sgs Microelettronica Spa | Metodo di progettazione di microcalcolatori integrati e microcalcolatore integrato a struttura modulare ottenuto con il metodo suddetto |
KR900007231B1 (ko) * | 1986-09-16 | 1990-10-05 | 가부시키가이샤 도시바 | 반도체집적회로장치 |
US4816422A (en) * | 1986-12-29 | 1989-03-28 | General Electric Company | Fabrication of large power semiconductor composite by wafer interconnection of individual devices |
US4868712A (en) * | 1987-02-04 | 1989-09-19 | Woodman John K | Three dimensional integrated circuit package |
JPH0834264B2 (ja) * | 1987-04-21 | 1996-03-29 | 住友電気工業株式会社 | 半導体装置およびその製造方法 |
US5016138A (en) * | 1987-10-27 | 1991-05-14 | Woodman John K | Three dimensional integrated circuit package |
US4918335A (en) * | 1987-11-06 | 1990-04-17 | Ford Aerospace Corporation | Interconnection system for integrated circuit chips |
US4858072A (en) * | 1987-11-06 | 1989-08-15 | Ford Aerospace & Communications Corporation | Interconnection system for integrated circuit chips |
JP2560805B2 (ja) * | 1988-10-06 | 1996-12-04 | 三菱電機株式会社 | 半導体装置 |
US4924291A (en) * | 1988-10-24 | 1990-05-08 | Motorola Inc. | Flagless semiconductor package |
US5255156A (en) * | 1989-02-22 | 1993-10-19 | The Boeing Company | Bonding pad interconnection on a multiple chip module having minimum channel width |
DE68926886T2 (de) * | 1989-09-15 | 1997-02-06 | International Business Machines Corp., Armonk, N.Y. | Designmethode für auf einem Träger angeordnete VLSI-Chips und resultierender Modul |
US5191404A (en) * | 1989-12-20 | 1993-03-02 | Digital Equipment Corporation | High density memory array packaging |
US5081563A (en) * | 1990-04-27 | 1992-01-14 | International Business Machines Corporation | Multi-layer package incorporating a recessed cavity for a semiconductor chip |
FR2680262B1 (fr) * | 1991-08-08 | 1993-10-08 | Gemplus Card International | Circuits integres pour carte a puce et carte a plusieurs puces utilisant ces circuits. |
US5212406A (en) * | 1992-01-06 | 1993-05-18 | Eastman Kodak Company | High density packaging of solid state devices |
US5340772A (en) * | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die |
US5325268A (en) * | 1993-01-28 | 1994-06-28 | National Semiconductor Corporation | Interconnector for a multi-chip module or package |
JPH07161919A (ja) * | 1993-12-03 | 1995-06-23 | Seiko Instr Inc | 半導体装置およびその製造方法 |
JP3269745B2 (ja) | 1995-01-17 | 2002-04-02 | 株式会社日立製作所 | モジュール型半導体装置 |
US6064116A (en) | 1997-06-06 | 2000-05-16 | Micron Technology, Inc. | Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications |
US6201186B1 (en) | 1998-06-29 | 2001-03-13 | Motorola, Inc. | Electronic component assembly and method of making the same |
US6418490B1 (en) * | 1998-12-30 | 2002-07-09 | International Business Machines Corporation | Electronic circuit interconnection system using a virtual mirror cross over package |
GB9915076D0 (en) * | 1999-06-28 | 1999-08-25 | Shen Ming Tung | Integrated circuit packaging structure |
US8554506B2 (en) * | 2009-08-07 | 2013-10-08 | Advanced Processor Srchitectures, LLC | Distributed computing |
US9645603B1 (en) | 2013-09-12 | 2017-05-09 | Advanced Processor Architectures, Llc | System clock distribution in a distributed computing environment |
US11042211B2 (en) | 2009-08-07 | 2021-06-22 | Advanced Processor Architectures, Llc | Serially connected computing nodes in a distributed computing system |
US9429983B1 (en) | 2013-09-12 | 2016-08-30 | Advanced Processor Architectures, Llc | System clock distribution in a distributed computing environment |
WO2013183011A2 (en) * | 2012-06-07 | 2013-12-12 | Intal Tech Ltd. | Electronic equipment building blocks for rack mounting |
JP6314591B2 (ja) * | 2014-03-27 | 2018-04-25 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
TWM577186U (zh) * | 2018-12-11 | 2019-04-21 | 品威電子國際股份有限公司 | Adapter for flexible cable |
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US3312771A (en) * | 1964-08-07 | 1967-04-04 | Nat Beryllia Corp | Microelectronic package |
US3483038A (en) * | 1967-01-05 | 1969-12-09 | Rca Corp | Integrated array of thin-film photovoltaic cells and method of making same |
US3568012A (en) * | 1968-11-05 | 1971-03-02 | Westinghouse Electric Corp | A microminiature circuit device employing a low thermal expansion binder |
US3611317A (en) * | 1970-02-02 | 1971-10-05 | Bell Telephone Labor Inc | Nested chip arrangement for integrated circuit memories |
US3641401A (en) * | 1971-03-10 | 1972-02-08 | American Lava Corp | Leadless ceramic package for integrated circuits |
US3777221A (en) * | 1972-12-18 | 1973-12-04 | Ibm | Multi-layer circuit package |
JPS49131863U (de) * | 1973-03-10 | 1974-11-13 | ||
DE2415047B2 (de) * | 1974-03-28 | 1978-02-02 | Siemens AG, 1000 Berlin und 8000 München | Multichip-verdrahtung mit anschlussflaechenkonfigurationen zur kontaktierung von vier gleichen halbleiterspeicher-chips |
US4038488A (en) * | 1975-05-12 | 1977-07-26 | Cambridge Memories, Inc. | Multilayer ceramic multi-chip, dual in-line packaging assembly |
JPS548976A (en) * | 1977-06-22 | 1979-01-23 | Nec Corp | Lsi package |
JPS5835367B2 (ja) * | 1978-07-18 | 1983-08-02 | ミツミ電機株式会社 | 回路素子基板及びその製造方法 |
US4297719A (en) * | 1979-08-10 | 1981-10-27 | Rca Corporation | Electrically programmable control gate injected floating gate solid state memory transistor and method of making same |
GB2056772B (en) * | 1980-08-12 | 1983-09-01 | Amdahl Corp | Integrated circuit package and module |
-
1981
- 1981-06-15 JP JP56091799A patent/JPS57207356A/ja active Granted
-
1982
- 1982-06-10 EP EP82303014A patent/EP0067677B1/de not_active Expired
- 1982-06-10 DE DE8282303014T patent/DE3277268D1/de not_active Expired
- 1982-06-15 US US06/388,616 patent/US4578697A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4225154A1 (de) * | 1992-07-30 | 1994-02-03 | Meyerhoff Dieter | Chip-Modul |
Also Published As
Publication number | Publication date |
---|---|
JPS6347143B2 (de) | 1988-09-20 |
JPS57207356A (en) | 1982-12-20 |
EP0067677A3 (en) | 1984-10-03 |
DE3277268D1 (en) | 1987-10-15 |
US4578697A (en) | 1986-03-25 |
EP0067677A2 (de) | 1982-12-22 |
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