EP0038002A2 - Dispositif d'affichage de caractères sur un écran - Google Patents

Dispositif d'affichage de caractères sur un écran Download PDF

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Publication number
EP0038002A2
EP0038002A2 EP81102581A EP81102581A EP0038002A2 EP 0038002 A2 EP0038002 A2 EP 0038002A2 EP 81102581 A EP81102581 A EP 81102581A EP 81102581 A EP81102581 A EP 81102581A EP 0038002 A2 EP0038002 A2 EP 0038002A2
Authority
EP
European Patent Office
Prior art keywords
memory
characters
data words
screen
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP81102581A
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German (de)
English (en)
Other versions
EP0038002A3 (en
EP0038002B1 (fr
Inventor
Ivan Furjanic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25784861&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP0038002(A2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0038002A2 publication Critical patent/EP0038002A2/fr
Publication of EP0038002A3 publication Critical patent/EP0038002A3/de
Application granted granted Critical
Publication of EP0038002B1 publication Critical patent/EP0038002B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • the invention relates to an arrangement for displaying characters on a screen of a display unit, in which the characters are displayed on the screen line by line, in which an image repetition memory is read out periodically and in which an image generator is provided which uses the forms of a character generator Data words assigned to characters are generated.
  • DE-PS 25 40 734 an arrangement for displaying characters on a screen of a display unit is known, in which the characters to be displayed are encoded by code characters stored in a data memory.
  • An image control unit calls the code characters from the data memory in a periodic sequence, corresponding to 50 or 60 image changes per second.
  • the image control unit contains a character generator in which data words associated with the forms of the characters that can be displayed on the screen are stored. Depending on the characters to be displayed on the screen, the corresponding data words are read from the character generator and fed to the display unit as line signals. If the display unit is designed as a cathode ray tube, the line signals represent video signals with which the electron beam is blanked.
  • the image repetition memory is designed as a shift register.
  • the code characters assigned to the characters to be displayed continuously circulate according to the frame rate.
  • the code characters each representing one line are read from the shift register.
  • the code characters are also fed to a character generator which outputs data words assigned to the shapes of the characters.
  • the video signals for the display unit designed as a cathode ray tube are generated using the data words.
  • a line grid is specified for the representation of the characters, which is formed in each case from several lines and which cannot be changed. Furthermore, the characters can only be displayed at specified character spaces.
  • the invention is therefore based on the object of specifying an arrangement for displaying characters on the screen of a display unit, in which the characters can be displayed in any line grid and at any point on the screen.
  • the object is achieved in the arrangement of the type mentioned in the introduction in that the image repetition memory is arranged in the connection path between the image generator and the display unit, that the image repetition memory is designed as a pixel memory provided with a memory, that each pixel on the screen a memory element of the memory is assigned and that the data words can be stored in the memory elements of the memory at any address.
  • the arrangement according to the invention has the advantage that the characters can be displayed at any point on the screen independently of a line grid.
  • Image generator reads the code characters of the characters to be displayed and their coordinates from the main memory of a central controller. With the help of the character generator, the data words assigned to the code characters are generated and stored in the pixel memory in such a way that the coordinates correspond to the addresses. If the main memory is part of a microcomputer system and is connected to the image generator via the data bus, the arrangement has the further advantage that the data bus is loaded much less than if the main memory, as in the known one. Arrangement, would also serve as a refresh memory. Furthermore, the arrangement has the advantage that graphic elements can also be displayed in a simple manner at any point on the screen.
  • a link unit is connected upstream of the memory in the pixel memory, by means of which the data words can be linked to data words previously read out from corresponding memory elements of the memory before they are stored in the memory.
  • the memory is preferably operated in a "read-modify-write" operating mode. In this operating mode, the stored information is first read out in each storage cycle, and it is possible to change it before the information is stored again. The change is made using the link unit.
  • the arrangement requires particularly little effort if the logic unit is designed as an arithmetic and logic control unit and as a function of supplied control signals performs different combinations.
  • Artithmetic and logic control units of this type are commercially available as integrated circuits.
  • the memory in the pixel memory is designed as a shift register.
  • the data words are stored and extracted in an advantageous manner if the memory is designed as a semiconductor memory with random access.
  • the arrangement requires little effort in particular if the memory is designed as a dynamic MOS memory with random access.
  • the stored information must be refreshed again at the latest after a predetermined period of time.
  • no special measures are required for refreshing if the refreshing of the data words stored in the memory is carried out by the periodic readout when the characters are displayed on the screen.
  • the pixel memory contains a parallel-to-serial converter, the parallel inputs of which are connected to the outputs of the memory and the output of which is connected to the display unit.
  • the pixel memory contains a time control unit, the control signals for the storage of the data words in the memory, the periodic reading of the data words from the memory and the synchronization of the display unit.
  • the telecommunications device shown in FIG. 1 is controlled by a microprocessor MP.
  • An interruption control IS and, on the other hand, a programmable control unit for direct memory access DMA (direct memory access) are connected to the microprocessor MP.
  • a primary memory PS, a secondary memory SS, a keyboard TA, a printer DR, a communication part KT and an arrangement for displaying characters on the screen BS of a display unit AZ are connected via a data bus DB and possibly an address bus.
  • the primary memory PS is designed as a semiconductor memory and it serves as a program memory and working memory.
  • the secondary memory SS can be designed as a floppy disk memory and / or as a magnetic bubble memory.
  • the keyboard TA contains keys for entering alphanumeric characters and function keys for performing various functions.
  • the printer DR is designed in a known manner and contains a type or a mosaic printing unit.
  • the communication part KT is connected to a long-distance line FL and contains transmission units for transmission by means of Keyboard TA of entered characters or stored characters and for receiving characters.
  • the arrangement for displaying characters on the screen BS of a display unit AZ contains, in addition to the display unit AZ, an image generator BG and a pixel memory BP.
  • code characters assigned to these characters are transmitted from the primary memory PS or from the secondary memory SS via the data bus DB to the image generator BG.
  • the image generator BG contains a character generator ZG, which contains data words assigned to the shape of the characters in a manner known per se. Depending on the code characters, the corresponding data words are read from the character generator ZG and transferred to the pixel memory BP.
  • a memory element of a memory SP provided in the pixel memory BP is assigned to each pixel on the screen BS. The data words are stored in these storage elements.
  • the image point memory BP serves as an image repetition memory and from it the data words corresponding to an image change frequency of approximately 50 or 60 image changes per second are read out and transmitted to the display unit AZ.
  • the screen BS of the display unit AZ can be designed as a screen of a cathode ray tube. In this case, a video signal is generated from the data words, with which the electron beam is palpated. If the screen BS is formed from individual picture elements, the data words are supplied to these picture elements.
  • the characters on the screen BS are displayed line by line and the characters to be displayed are from image. points put together, which are arranged on these lines.
  • a character space is formed from 6x12 pixels and the characters are displayed within the character space in a basic grid of 5x7 pixels.
  • the memory capacity of the memory SP provided in the pixel memory BP is 512x256 bits, so that the characters can be displayed in 21 lines with 85 characters each on the screen BS.
  • the image generator BG shown in FIG. 2 contains a control unit ST, which is also designed, for example, as a microprocessor system.
  • the control unit ST is connected on the input side to the data bus DB.
  • the code character CZ assigned to this character is transmitted to the image generator BG via the data bus DB.
  • the control unit ST switches the code character CZ through to the character generator ZG, in which data words DW associated with the shape of the character are stored.
  • the character is formed in raster lines, with each raster line corresponding to a data word DW.
  • address signals which are assigned to the coordinates of the character on the screen BS are transmitted via the data bus DB. These coordinates are buffered in two registers XAR and YAR.
  • the pixel memory BP contains a time control unit ZS, which transfers the data words DW into the memory SP provided in a memory unit SPE, reads out the data words DW from the memory SP for generating the video signal VS and. controls generation of signals SV and SH for vertical and horizontal synchronization of the display unit AZ.
  • ZS time control unit
  • the data words can be transferred to the storage unit SPE line by line or character by character.
  • the data words DW assigned to a line become the characters represented in one line transfer.
  • the data words DW assigned to a character are transmitted one after the other in time. The transmission expediently takes place after the display of a line or a complete image on the screen BS. This is determined by a signal S1 emitted by the time control unit ZS.
  • a processing unit ALU is connected upstream of the memory SP to manipulate the data words stored in the memory SP.
  • This processing unit is designed, for example, as a commercially available arithmetic and logical control unit. It links the signals at its inputs according to arithmetic or logical functions. The type of linkage is determined by control signals S2 which are output by the control unit ST.
  • the data words DW1 in the storage unit sP2 are fed to a parallel-to-serial converter, which generates the video signal VS after a parallel-to-serial conversion of the data words DW1 and outputs it to the display unit AZ.
  • the memory unit SPE contains a dynamic MOS memory with random access as the memory SP.
  • the memory SP has a storage capacity of 18 KB for displaying 512x256 pixels on the display unit AZ.
  • the memory SP is organized in bytes, so that its address space comprises 18K.
  • the low-order address bits are represented by the address signals A2.
  • the address signals A1 and A2 are fed to a multiplexer MX1.
  • the multiplexer MX1 switches through the address signals A1 and A2 to a multiplexer MX2. The switching takes place by means of a signal SZ emitted by the time control unit ZS during the line return and / or the image return of the electron beam.
  • an MX2 With a signal S3, an MX2 first switches through the least significant bits as the row address and then the more significant bits as the column address of the memory SP.
  • the time control unit ZS sends signals ZA and SA to the memory SP, with which it is communicated that the address present in each case is a row or a column address.
  • a write signal SB is emitted.
  • the data word output by the image generator BG is then stored in the memory SP at the point identified by the address signals A1 and A2.
  • the time control unit ZS contains a counter which generates address signals AD, which call the memory elements of the rows of the memory SP in succession in a cyclical order and those of the individual columns within the rows.
  • AD address signals
  • the signal SZ switches the signals AD through to the output of the multiplexer MX1.
  • the time control unit ZS generates the signals S3, ZA and SA, so that the memory SP is read out line by line.
  • the stored data words are read out in parallel byte by byte and fed as signals DW1 to a parallel-series converter PSU.
  • the parallel-to-series converter PSU generates, under the control of a signal S4 from the data words DW1, the video signal VS, which is used for the scanning of the electron beam in the cathode ray tube of the display unit AZ.
  • the time control unit ZS simultaneously outputs the synchronization signals SV and SH to the display unit AZ.
  • the data words DW of a first character are first stored in the memory. After reading out the stored data words DW1, these are linked with the data words DW of the further character in the linking unit ALU in accordance with an OR link and stored in the corresponding location in the memory SP at which the data words DW1 were previously stored. In this way, the pixel sets of the two characters are combined so that the union of the pixels is displayed on the screen BS.
  • the memory SP is preferably operated in the "read-modify-write" operating mode, in which the stored information is first read out and then written to the same memory location after a change, if necessary.
  • the OR operation is also set using a signal S2.
  • this data word is linked to the data word DW output by the character generator ZG after reading out in accordance with an antivalence function.
  • the antivalence function is also set by a signal S2. It is also possible to display the characters on the screen inversely, so that the colors of the background or the characters are interchanged if the data words DW or DW1 are linked to a data word formed from pure binary values 1 in accordance with an antivalence function.
  • the memory SP can be understood as an image of the screen BS.
  • a memory element in the memory SP is assigned to each possible pixel on the screen BS. If if the electron beam is to be palpated at the location assigned to a possible pixel, a binary character with a first binary value, for example binary value 1, is stored in the corresponding memory element. In a corresponding manner, binary characters with the binary value 0 are stored at the points at which the electron beam is not palpated.
  • Each line of the memory SP corresponds to a line on the screen BS.
  • the characters can be displayed at any coordinates on the screen BS. These coordinates are identified by the address signals A1 and A2.
EP81102581A 1980-04-10 1981-04-06 Dispositif d'affichage de caractères sur un écran Expired EP0038002B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE3013706 1980-04-10
DE3013706 1980-04-10
DE3014437A DE3014437C2 (de) 1980-04-10 1980-04-15 Anordnung zum Darstellen von alphanumerischen Zeichen an einem Bildschirm einer Anzeigeeinheit
DE3014437 1980-04-15

Publications (3)

Publication Number Publication Date
EP0038002A2 true EP0038002A2 (fr) 1981-10-21
EP0038002A3 EP0038002A3 (en) 1982-06-23
EP0038002B1 EP0038002B1 (fr) 1986-09-24

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ID=25784861

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81102581A Expired EP0038002B1 (fr) 1980-04-10 1981-04-06 Dispositif d'affichage de caractères sur un écran

Country Status (4)

Country Link
US (1) US4433330A (fr)
EP (1) EP0038002B1 (fr)
CA (1) CA1190677A (fr)
DE (1) DE3014437C2 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0095618A2 (fr) * 1982-05-31 1983-12-07 Kabushiki Kaisha Toshiba Système de mémoire
FR2541806A1 (fr) * 1983-02-25 1984-08-31 Texas Instruments France Processeur d'affichage video en mode graphique
FR2541805A1 (fr) * 1983-02-25 1984-08-31 Texas Instruments France Systeme de visualisation de donnees sur un ecran video en mode graphique
EP0121453A1 (fr) * 1983-02-25 1984-10-10 TEXAS INSTRUMENTS FRANCE Société dite: Système de visualisation de données sur un écran vidéo en mode graphique
EP0145530A2 (fr) * 1983-10-18 1985-06-19 Digital Equipment Corporation Circuit de fourniture de données pour un système d'affichage de données
EP0170977A2 (fr) * 1984-08-06 1986-02-12 Honeywell Bull Inc. Sous-système d'affichage
EP0295943A2 (fr) * 1987-06-19 1988-12-21 Sekisui Jushi Kabushiki Kaisha Plat pour aliment

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216755A (en) * 1980-12-04 1993-06-01 Quantel Limited Video image creation system which proportionally mixes previously created image pixel data with currently created data
US4514818A (en) * 1980-12-04 1985-04-30 Quantel Limited Video image creation system which simulates drafting tool
GB8306339D0 (en) * 1982-03-19 1983-04-13 Quantel Ltd Video processing systems
US5459529A (en) * 1983-01-10 1995-10-17 Quantel, Ltd. Video processing for composite images
US4566000A (en) * 1983-02-14 1986-01-21 Prime Computer, Inc. Image display apparatus and method having virtual cursor
DE3425635A1 (de) * 1984-07-12 1986-01-16 Olympia Werke Ag, 2940 Wilhelmshaven Verfahren zur ansteuerung einer raster-aufzeichnungseinrichtung
JPS63225288A (ja) * 1987-03-16 1988-09-20 沖電気工業株式会社 文字表示装置
US5101196A (en) * 1988-11-10 1992-03-31 Sanyo Electric Co., Ltd. Display device for microcomputer
US20020140818A1 (en) * 2001-04-02 2002-10-03 Pelco System and method for generating raster video test patterns

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US4070710A (en) * 1976-01-19 1978-01-24 Nugraphics, Inc. Raster scan display apparatus for dynamically viewing image elements stored in a random access memory array
GB1529582A (en) * 1974-10-29 1978-10-25 Xerox Corp Data processing display system
FR2426294A1 (fr) * 1978-05-18 1979-12-14 Thomson Csf Generateur de signaux pour console graphique
FR2426295A1 (fr) * 1978-05-18 1979-12-14 Thomson Csf Generateur de symboles pour console graphique

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US3396377A (en) * 1964-06-29 1968-08-06 Gen Electric Display data processor
US3453384A (en) * 1965-12-07 1969-07-01 Ibm Display system with increased manual input data rate
US3453601A (en) * 1966-10-18 1969-07-01 Philco Ford Corp Two speed arithmetic calculator
US3675232A (en) * 1969-05-21 1972-07-04 Gen Electric Video generator for data display
US3675208A (en) * 1970-05-28 1972-07-04 Delta Data Syst Editing system for video display terminal
DE2758811C2 (de) * 1977-12-30 1979-05-31 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung für Matrixdrucker zum Erzeugen von Schriftzeichen nach dem Prinzip des Doppeldruckes
US4240073A (en) * 1978-05-15 1980-12-16 Thomas Electronics, Inc. Cathode ray tube display system with display location memory

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
GB1529582A (en) * 1974-10-29 1978-10-25 Xerox Corp Data processing display system
US4070710A (en) * 1976-01-19 1978-01-24 Nugraphics, Inc. Raster scan display apparatus for dynamically viewing image elements stored in a random access memory array
FR2426294A1 (fr) * 1978-05-18 1979-12-14 Thomson Csf Generateur de signaux pour console graphique
FR2426295A1 (fr) * 1978-05-18 1979-12-14 Thomson Csf Generateur de symboles pour console graphique

Non-Patent Citations (1)

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Title
Microprocessors and their Applications, 5th Euromicro Symposium on Microprocessing and Microprogramming, 28.-30. August 1979, seiten 59-62 Amsterdam, NL. H. ROETHLISBERGER: "Distributed Architecture for a Fast High Resolution Raster Scan Display" *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0095618A2 (fr) * 1982-05-31 1983-12-07 Kabushiki Kaisha Toshiba Système de mémoire
EP0095618A3 (en) * 1982-05-31 1987-02-25 Kabushiki Kaisha Toshiba Memory system
FR2541806A1 (fr) * 1983-02-25 1984-08-31 Texas Instruments France Processeur d'affichage video en mode graphique
FR2541805A1 (fr) * 1983-02-25 1984-08-31 Texas Instruments France Systeme de visualisation de donnees sur un ecran video en mode graphique
EP0121453A1 (fr) * 1983-02-25 1984-10-10 TEXAS INSTRUMENTS FRANCE Société dite: Système de visualisation de données sur un écran vidéo en mode graphique
EP0145530A2 (fr) * 1983-10-18 1985-06-19 Digital Equipment Corporation Circuit de fourniture de données pour un système d'affichage de données
EP0145530A3 (fr) * 1983-10-18 1989-07-26 Digital Equipment Corporation Circuit de fourniture de données pour un système d'affichage de données
EP0170977A2 (fr) * 1984-08-06 1986-02-12 Honeywell Bull Inc. Sous-système d'affichage
EP0170977A3 (fr) * 1984-08-06 1988-03-16 Honeywell Bull Inc. Sous-système d'affichage
EP0295943A2 (fr) * 1987-06-19 1988-12-21 Sekisui Jushi Kabushiki Kaisha Plat pour aliment
EP0295943A3 (fr) * 1987-06-19 1990-03-21 Sekisui Jushi Kabushiki Kaisha Plat pour aliment

Also Published As

Publication number Publication date
EP0038002A3 (en) 1982-06-23
EP0038002B1 (fr) 1986-09-24
DE3014437C2 (de) 1982-05-27
CA1190677A (fr) 1985-07-16
US4433330A (en) 1984-02-21
DE3014437A1 (de) 1981-10-22

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