EP0030034B1 - Digitale Halbleiterschaltung für eine elektronische Orgel - Google Patents

Digitale Halbleiterschaltung für eine elektronische Orgel Download PDF

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Publication number
EP0030034B1
EP0030034B1 EP80107529A EP80107529A EP0030034B1 EP 0030034 B1 EP0030034 B1 EP 0030034B1 EP 80107529 A EP80107529 A EP 80107529A EP 80107529 A EP80107529 A EP 80107529A EP 0030034 B1 EP0030034 B1 EP 0030034B1
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EP
European Patent Office
Prior art keywords
output
input
gate
counter
assigned
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EP80107529A
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German (de)
English (en)
French (fr)
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EP0030034A3 (en
EP0030034A2 (de
Inventor
Helmut Rösler
Klaus-Dieter Dipl.-Phys. Bigall
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H5/00—Instruments in which the tones are generated by means of electronic generators
    • G10H5/02—Instruments in which the tones are generated by means of electronic generators using generation of basic tones
    • G10H5/06—Instruments in which the tones are generated by means of electronic generators using generation of basic tones tones generated by frequency multiplication or division of a basic tone
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H1/00—Details of electrophonic musical instruments
    • G10H1/18—Selecting circuits
    • G10H1/183—Channel-assigning means for polyphonic instruments

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  • the invention relates to a digital semiconductor circuit for an electronic organ with a number of control inputs applied to the manual corresponding to the number of play keys of the manual of the organ and with a number of sound signal inputs applied by an oscillator system with periodic electrical oscillations, in each of which one control input each Game key of the manual and one audio signal input each is assigned a fixed audio frequency, in which an audio signal output is also provided for the application of an electro-acoustic transducer and in which the control signals serving for the control inputs finally correspond to the logic levels.
  • control inputs are acted on by each of these control inputs being able to be applied via a switch to a common first operating potential assigned to the level “1, and when the individual game button is actuated, the associated switch is closed as a result of the actuation.
  • Control inputs whose game buttons are pressed have the level «1 •
  • control inputs whose game buttons have not been pressed have the level « 0 »accordingly.
  • a generator is used to generate the sound frequencies, which - starting from an oscillator delivering a square wave with the highest frequency corresponding to the two logic levels - delivers the individual tone vibrations by frequency division at least to the highest octave of the organ and to one input each provides an AND gate with two inputs, the second input of which is acted upon by the associated control input. The entirety of these AND gates is then provided to act on the audio signal outputs.
  • the individual control inputs are each assigned to a cell of a clock-controlled shift register and operated as a parallel series converter, and that both the signal output of the shift register and the clock pulses provided for its operation serve to control a switching system which serve the entirety the intended sound signal inputs and the sound signal outputs,. the number of which is lower than the number of control inputs, that each of the sound signal outputs is assigned an amplitude shaper and that finally the outputs of the amplitude shifters are connected to an electro-acoustic transducer.
  • the aim is to only release it again when the sound, and thus the electrical information causing the sound, in the amplitude shaper affected by the sound signal output has decayed after the play key causing the assignment has been released.
  • a reverberation effect is provided so that the sound played is not suddenly suppressed when the play button is released.
  • the new tone is to be generated via the tone signal output that has been released by releasing the other game button. If several game buttons are released at the same time when the audio signal outputs are fully occupied and a new game button is pressed, the information associated with the new game button and the audio signal that it calls up should be applied to the audio signal outputs that this frees up, in which the tone that was played last and still remains in the reverberation effect faded most. If a released game button is finally struck again immediately, it is advisable to reassign the old sound signal output to the switching system.
  • FIGS. 1 to 10 the essential parts of the invention are shown in the block diagram, while the remaining figures deal with details of the switching system and the amplitude shaping.
  • n control inputs E 1 , E2,... E n , or in short E v , of the semiconductor digital circuit according to the invention are now acted upon by the individual game keys of the manual M.
  • These n control inputs E v form the information input for each register cell of a clock-controlled shift register PSW, which is operated as a parallel series converter and is supplied by a clock generator TG with the shift clocks required for pushing out the information supplied by the manual M during the individual query cycles.
  • the shift register PSW preferably has n register cells, so that each control input E v has a register cell and each register cell has a control input E v control input E v of the shift register PSW.
  • the data output DA of the shift register PSW is connected to the data input DE of a so-called channel selector KW, which at the same time forms an information input of the switching system VM.
  • the switching system contains the count input of a sound address counter TAZ, which is designed as a digital counter on a binary basis and is described in more detail with regard to its design and control.
  • the switching system VM p contains mutually identical output parts, that is to say output channels V, to Vp, which are controlled on the one hand by the channel selector KW and on the other hand by the sound address counter TAZ.
  • the switching system has m audio signal inputs, which are acted upon by an audio frequency generator TOS.
  • the tone frequency generator TOS is designed in the usual way and has a number of tone frequency outputs, each of which is assigned to a tone frequency.
  • the tone frequency generator TOS usually has twelve tone frequency outputs, each of which provides a periodic square wave with a frequency that is assigned to a tone of the highest octave of the range of the organ.
  • the individual sound signal input TSE of the switching system VM is connected to an input (designated in the same way) of each of the mutually identical output channels V, or V 2 ,... Or Vp.
  • Each of these output channels V, to Vp is provided with means which allow a reduction of the square waves delivered by the tone frequency generator TOS to the frequencies of the corresponding tones in the lower octaves.
  • these output channels V 1 to Vp are each provided with an audio signal output AU 1 , AU 2 , ... AUp, from which the audio signals selected via the 2 Manual M are applied to the downstream amplitude formers AF, or AF 2 , ... or AF P violate.
  • the output of the individual amplitude shaper AF 1 or AF 2 , ... or AFp is z. B. in the manner shown in FIG. 6 for controlling a common electro-acoustic transducer, that is, a loudspeaker system.
  • each of the mutually identical output channels V 1 or V 2 ,... Or Vp has a further output B 1 . or B 2 , ... or Bp, via which there is a reaction on the channel selector KW on the one hand, and on the other hand an additional control of the respectively associated amplitude shaper AF 1 or AF 2 , ... or AFp.
  • the tone address counter TAZ consists of two parts.
  • the first part consists of four flip-flop cells connected in series in a known manner, e.g. B. from toggle flip-flop cells, each representing a binary counter.
  • the counting stages are switched in such a way that the first part of the counter counts up to " 12 ", so that when the thirteenth counting pulse arrives, it is already switched back to the initial state "0" simultaneously with the arrival of the thirteenth counting pulse (and only every thirteenth counting pulse) a counting pulse is given to the second part of the sound address counter TAZ.
  • the second part of the sound address counter TAZ consists of three flip-flop cells connected in series and thus of three counting stages. They are switched in such a way that the highest count corresponds to the total number of octaves provided and is therefore preferably "6 or" 7.
  • the easiest way to achieve the above-mentioned behavior of the tone address counter TAZ is to include those outputs of the four flip-flop cells forming the first counter portion, which therefore show a " 1 " at 12 at the desired highest count, with one input of an AND gate connects four inputs so that when the highest count is reached, a «1» also appears at the output of the AND gate. This is then fed to the reset input of the first part of the sound address counter TAZ and to the counting input of the second part of the sound address counter.
  • the individual counting states of the first part of the counter TAZ are dedicated to the individual tones within the individual octaves and the individual counting states of the second part are each dedicated to an octave in the range of the organ.
  • the total number of register cells corresponds to the number of game keys in the manual M.
  • Each register cell has its own information input, which is connected via a clock-controlled transfer gate to the control input E v of the digital semiconductor circuit, each of which is supplied with logic information from the manual M. which is assigned to the relevant register cell by PSW.
  • the entirety of the transfer gates mentioned is controlled by a takeover clock UE, which is also provided by the clock generator TG which supplies the shift clocks T and thus the counting clocks for the counter TAZ.
  • a takeover clock UE which is also provided by the clock generator TG which supplies the shift clocks T and thus the counting clocks for the counter TAZ.
  • a read-write memory forms an essential part of each of these output parts of the switching system VM.
  • this memory also consists of two parts, namely a part S and a part S * .
  • the first part S receives its information on the basis of the part of the address counter TAZ assigned to the individual sound names, the second storage part S * , on the other hand, is supplied with information to be stored due to the effect of the second part of the sound address counter TAZ assigned to the octaves.
  • the information read out from the first memory part S is sent via a first decoder D to twelve AND gates U 1 to U 12 ' which are simultaneously acted upon by the entirety of the audio frequency inputs TSE, while the information obtained from the second memory part S * is used to act on a second decoder D *. are provided.
  • the information provided from the two memory parts is used to control a NOR gate NR, which in turn controls the smoke input B 1 or B 2 ... or Bp of the output part V 1 or V 2, etc., already mentioned when looking at FIG. 1 . forms.
  • each takeover clock UE which inputs the information into the input shift register PSW
  • the serial readout of the respectively recorded information from this shift register and the structure of the information relating to the two memory parts S and S * commence in a manner to be described.
  • Each of the two memory parts is expediently made up of discrete memory cells, in particular of discrete quasi-static register cells corresponding to the input shift register PSW, the clock pulses TM for the input shift register PSW or the counting clocks for the sound address counter TAZ as shift clocks for the construction of the memory content of both memory parts S and S * are used, as will be explained in more detail with reference to FIG. 3.
  • the data output DA of the input shift register PSW can be connected to the one input of an AND gate for this purpose place, whose other input is controlled by the shift clocks T or by secondary pulses derived therefrom.
  • the output of this AND gate only delivers a “1” if a “1” passes through the data output DA of the input shift register PSW.
  • the bits appearing at the output of the AND gate and assigned to the individual shift clock pulses arrive at the information input of the first memory part S and at the information input of the second memory part S *.
  • the effect of clock sequences derived from the shift clocks or in some other way ensures that the “1 in the first memory part S in the memory cell assigned to the position corresponding to the sound being played within the octave and in the second memory part S * in that of the sound played containing the memory cell associated with the octave.
  • the respective stored contents of the two memory parts are erased by a common residual pulse, which is advantageously identical to the takeover pulses UE regulating the information input into the input shift register. Further details regarding the information input into the two memory parts S and S * of the individual output parts V 1 ... Vp are brought up in connection with FIG. 3.
  • a decoder D or D * is assigned to each of the two memory parts S and S * .
  • the first memory part S which is used to hold the 4-bit word forming the sound address within the individual octave, accordingly consists of four individual shift register cells, which are evaluated in parallel via the decoder D - a “one-out-of-twelve decoder”. Accordingly, the first decoder D, which has twelve signal outputs and has twelve signal outputs corresponding to the 12 tone names, c, cis, d, dis, is assigned one AND gate U 1 or U 2 ,... Or U 12 for each signal output. Each of these AND gates has two inputs.
  • the second input is each connected to one of the twelve sound signal inputs TSE in a manner already indicated, which in turn are acted upon by one of the twelve sound frequency outputs of the sound frequency generator TOS and thus each with one of the sound frequencies of the highest octave.
  • the output of each of the AND gates U 1 to U 12 is connected to an output of a common OR gate O.
  • the second memory part S * is acted upon by a 3-bit word forming the address of the octave selected in each case by the actuated play key and likewise controls a decoder D * in parallel operation .
  • This is designed as a “1-out-of-six decoder” and accordingly has six signal outputs, of which only one receives the level “1” due to the information present in the memory section S * .
  • the second memory section S * With any number q of the octaves provided in the manual, it can be determined that the second memory section S * then has q memory cells, that is to say shift register cells, which act as a «one-out q decoder »D * are formed, and then this decoder D * q controls the AND gates U 1 * to U o * .
  • a total of 6 octaves are provided in the manual M, so that the memory section S * has only three information outputs leading to the decoder D * and the latter is designed as a “one-of-six” decoder.
  • Each of the q outputs of the second decoder D * is assigned one of q AND gates U 1 * , U 2 * , ... U o * in that the decoder output in question is connected to one of the two inputs of the AND gate U 1 assigned to it * is connected to U o * , while the other input of the relevant AND gate is acted upon via a frequency divider TT controlled by the first OR gate 0 controlled by the first decoder D and the tone generator TAZ.
  • the entirety of the * acted upon by the second decoder D AND gate U 1 to U * o * lies with their signal outputs at a respective input of a second OR gate O *, the signal output of the tone signal output AU 1 and AU 2, ... or AU P forms when the considered output part of the switching system VM is its first output part V 1 or its second output part V 2 ... or its last output part Vp.
  • the frequency divider TT controlled by the first OR gate 0 is henceforth referred to as a tone divider, since it has the task of frequency dividing the tone signals belonging to the tones of the highest octave and supplied by the tone generator TOS, for the output AU 1 or: AU 2 . .. or AUp to generate certain tone vibrations.
  • Each of the * is controlled by the second decoder D AND gate U 1 to U o * - that in the example U 1 * to U 6 * - is controlled at its second input via the first OR gate 0 and in the following way:
  • the output of the first OR gate 0 is not only at the input of the sound divider TT but also at the second input of the first of the AND gates U i * mentioned.
  • each of these * is controlled by the second decoder D AND gate U 1 is U * to * o assigned to each one of the foreseen in the Manual M octaves.
  • the tone selected in each case is supplied as the tone of the highest octave to the AND gate U 1 * and to the tone divider TT via the decoder D.
  • the addressing of the octave selected via the manual M stored in the second memory section S * then activates only one of the AND gates U 1 * - Uq * , that is to say in the example case U 1 * - U 6 * , so that when U 1 * the selected tone of the highest octave, when activating U 2 * the selected tone of the second highest octave and when activating U o * the selected tone from the lowest octave to the second OR gate 0 * and thus to the signal output AU of the relevant output channel - if this has been selected by a corresponding signal via its control input UE 1 or UE 2 or .... UE P from the channel selector KW.
  • a control input B 1 or B 2 or ... or Bp signals required for the feedback control on the channel selector KW and for influencing the amplitude shaper AF 1 to AFp downstream of the respective output part V 1 -Vp, as already indicated in FIG. 1, a control input B 1 or B 2 or ... or Bp signals required.
  • each -the * controlled by the two memory parts S and S input of the decoder D and D * is connected to one input of a NOR gate NR, the only a signal via the return control input B 1 'or B 2 etc. gives up when the two memory parts S and S * of the output channel V 1 and V 2 etc. are empty.
  • a comparison is also provided between the signal input and the signal output of each of the memory cells of the two memory parts of the individual output channel V 1 to Vp.
  • This can e.g. B. via an equivalence gate E 1 or E2 or .... or .... Ep (in the example case E 10 ), the outputs of which are each at an input of an AND gate UL with p inputs at one input of an AND -Gatters UL with p inputs (i.e. in the example with 10 inputs) happen.
  • the entirety of these equivalence gates with the AND gate forms a comparator K 1 or K 2 , etc.
  • a “1” at the output of the AND gate UL indicates that the sound address stored in the relevant output channel V 1 to Vp is equal to the counter reading of the sound address counter TAZ.
  • the gates E 1 to Ep can all also be exclusive OR gates. However, the AND gate UL must then be replaced by a corresponding NOR gate.
  • the task of the comparators K 1 to Kp is, as the further considerations will show, diverse. One of the tasks is to indicate that the relevant output channel V 1 to Vp is occupied. A common task of these comparators is to control the KW channel selector. This takes place with the intermediation of an OR gate OD * , as can be seen from FIG. 3.
  • the various functions that are to be performed by the switching system VM are primarily controlled via the channel selector KW.
  • the block diagram of a preferred embodiment of the channel selector KW is shown in FIG. 3.
  • Each of the intended output channels V 1 to Vp is assigned an AND gate A 1 or A 2 or ... or Ap (in the example case A 1 to A 10 ) in the channel selector KW.
  • Each of these AND gates A 1 to Ap is controlled via two inputs, of which one at the data input DE of the channel selector controlled by the input shift register PSW and the other at the output of an OR gate OD 1 or OD 2 or respectively. .. or OD P lies.
  • the signal output of each of these AND gates A 1 to Ap forms the control output UE 1 or UE 2 or UEp, which is used for additional control of the associated output part V 1 or V 2 or ... or V P of the switching system VM each associated address memory S and S * is used, which will be discussed in more detail.
  • the OR gates OD 1 or OD 2 or ... or OD P which control the individual AND gates A 1 to Ap just mentioned have a first input, each of which is controlled by the output of a further AND gate UG 1 or UG 2 or ... or UGp is applied immediately.
  • a second signal input of each of these OR gates OD 1 to ODp is controlled by the signal output of a further AND gate A * 1 to A * p.
  • the AND gates UG 1 to UG P mentioned in connection with the control of the OR gates OD 1 to ODp have three inputs, with the exception of the AND gate UG 1 assigned to the first output part or channel V 1 , while that to the first channel V 1 assigned AND gate has only two inputs.
  • One of the inputs of all of these AND gates UG 1 to UGp is through the control output B 1 or B 2 or Bp of the relevant output part or channel V 1 or V 2 or Vp (given by NOR gate NR) controlled while another input of each of these AND gates via an inverter IV is controlled by a common NOR gate NO.
  • the first output part V 1 associated AND gate UG 1 is therefore fully controlled by the control output B 1 and by the NOR gates NO.
  • the remaining AND gates from the group of AND gates UG 1 to UGp have, as just stated, three inputs, two of which are controlled in an analogous manner to the two inputs of the first of these AND gates UG 1 . Accordingly, there is one input of each of these AND gates UG 2 to UGp at the output of NOR gate NO via inverter IV and a second input at control output B 2 or B 3 or ... or Bp of the respective associated output part V 2 or V 3 or ... or Vp of the switching system VM.
  • the third input of these AND gates UG 2 to UGp is via the output of a logic cell L 12 or L23 or ... or L (P-2), (p-1) or . L (p-1), p controlled.
  • the logic cell L 12 which is provided for controlling the third input of the second AND gate UG 2 from the series of AND gates UG 1 to UG P , consists only of an inverter, the input of which is through the control output B 1 of the first output part V , the switching system VM is controlled (which is also at the one input of the AND gate UG 1 ) and its output is connected on the one hand to the third input of the AND gate UG 2 (assigned to the second output part V 2 ) and on the other hand at the input of next logic cell L 23, which is provided for loading the following AND gate UG 3 .
  • the remaining logic cells L 23 to L (p-1), p are identical to one another and each consist of an inverter L 23a or L 34a or ... or L (p-1), pa and a NOR gate with two Inputs, the output of which forms the signal output of the logic cell concerned and which is designated L 23b , L 34b , ... L (p-1) pb (see FIG . 4).
  • the output of the NOR gate NO not only causes the AND gates UG 1 to UGp that have just been discussed, but also another group A 1 * to Ap * controlled by AND gates, which are also each assigned to one of the output channels V 1 to Vp of the switching system VM.
  • Each of these AND gates A 1 * to Ap * z. B. has two inputs, one of which is directly connected to the output of the NOR gate NO without the interposition of an inverter or another component, while the other is located at the output of a comparator K 1 * to Kp * .
  • the structure of the comparators K 1 * to Kp * corresponds to that of the individual comparators K 1 to Kp.
  • the mode of operation of the channel selector KW shown in FIGS. 3 and 4 will now be described. It is useful to go into the formation of the individual memory parts S and S * in the individual output channels V 1 to Vp. It is recommended that the individual memory cells of these memory parts are formed from quasi-static shift register cells. In contrast to a write register, however, no series connection of the memory cells is provided here, but each memory cell is provided for itself both on the input side and on the output side. All that is common is the loading via the manual M and the clock supply.
  • the signal outputs of the first storage part S forming memory cells S 1 to S are still 4 to S 3 are provided for acting on the first decoder D and the outputs of the second storage part S * forming memory cells S 1 * for control of the second decoder D *.
  • the remaining memory cells S 4 or S 1 * to S 3 * correspond in full to the memory cells shown in FIG.
  • Each of the memory cells of the two memory parts S and S * in each output channel V 1 to Vp contains four transfer transistors t 1 , t 2 , t 3 and t 4 , each of which is provided by an enhancement-type MOS transistor. It also contains an inverter 1 and a NOR gate N.
  • a so-called three-phase clock generator that is to say a clock generator TG, which is capable of delivering three periodic pulse trains TM, TS and TSS having the same frequency, is required. It is essential for the three pulse sequences that the individual pulses TS are arranged without overlap between two pulses of the sequence TM, so that a space is provided between each of the adjacent pulses TM and TS.
  • the falling edges of the pulses from the sequence TSS coincide with the falling edge of one pulse each from the sequence TS while the pulses TSS are slightly delayed with respect to the pulses TS with respect to the rising edge.
  • the input shift register PSW is also expediently constructed using quasi-static register cells, that is to say with cells corresponding to FIG. 5, the clocks TM, TS and TSS are also required here.
  • the individual counter stages of the sound address counter TAZ and other counters used in the circuit in particular also the reference counter RZ and the age counter AZ 1 to AZp, are built up by means of master-slave flip-flops (in particular by means of one toggle flip-flop each) , for which the Impulse TM and TS are also required.
  • the data input of each of the memory cells forming the memory parts S and S * is formed by the source terminal of the transfer transistor t 1 , which is accordingly connected to the counting output Q of the counter stage of the sound address counter TAZ assigned to it.
  • the gates of the input transfer transistors t 1 of all of these memory cells S 1 to S 4 and S 1 * to S 4 * are together at the output of the channel selector outputs UE 1 and UE 2 assigned to the respective output channel V 1 to Vp and controlling them or ... or UEp-forming AND gates A 1 or A 2 or ... or Ap.
  • the AND gates A 1 to Ap must be equipped with three signal inputs each. Two of them are acted on in the manner shown in FIG. 3, while the third is controlled by the clocks TM controlling the memory cells S 1 ' S 2 etc.
  • the drain of the transistor t 1 of each of these memory cells S 1 ' S 2 etc. lies on the one hand at the input of an inverter I, on the other hand on one current-carrying electrode of two transfer transistors t3 and t4.
  • the output of the inverter is connected via a transfer transistor t2 to the one input of a NOR gate N, the second input of which is controlled by a general reset signal Re and the output of which forms the output of the relevant memory cell.
  • the gates of the transfer transistors t2 of the memory cells are controlled together by the clock TS.
  • the transfer transistors t3 bridge with their source-drain path the series circuit of inverter I, transfer transistor t2 and NOR gate N. Their gate is controlled by the clock pulses TSS.
  • the transfer transistor t4 lies with its source-drain path between the reference potential (ground) and the input of the inverter I. Its gate is acted upon by pulses L generated in a manner to be described.
  • the output of the NOR gates N of each of the memory cells S 1 ' S 2 etc. is on the one hand connected to the input of one of the two decoders D or D * assigned to it.
  • each of the seven memory cells is assigned one of the comparison gates E 1 to E 7 of the comparator K 1 or K 2 etc.
  • one input of the relevant equivalence gate E 1 or E2 or ... or E 7 of the comparator K 1 ' K 2 ... Kp in question is connected to the source connection of the input transfer transistor t 1 and the other input to the Output ⁇ of the NOR gate N of the memory cell concerned.
  • the erase pulses L controlling the gate of the transistors t 4 are given by pulses selected from the sequence TM. Their generation is still being discussed.
  • the “1” that arrives at the source of the input transfer transistor t 1 assigned to the individual memory cells in the memory parts S and S * of the individual output channel V 1 to Vp is obtained in the respective memory cell due to the two clock sequences TS and TSS until an erase pulse L erases the "1" via the erase transistor t4 and the memory cell is thus again available for writing a "1". Since the erase pulse L reaches all the erase transistors t4 of the memory cells S 1 ' S 2 , etc. associated with the respective output channel K 1 to Kp etc., the two memory parts S and S * of the respective output channel are erased simultaneously, so that the channel is re-exposed through the sound address counter TAZ. This is indicated by the "1" on the control output S 1 ' S 2 etc. of the relevant channel V 1 , V 2 , ...
  • a general reset signal ensures that all output channels V 1 to V P , the age counters AZ 1 to AZ P assigned to them and the reference counter RZ are in the initial state, so that a “1” is given at the output of all comparators K 1 to K P and K 1 * to Kp * .
  • each of the inputs on one of the AND gates A 1 to Ap must be assigned a «1. Since the information from the input shift register PSW is also shifted by the clock pulses TM, TS and TSS provided by the clock generator TG when the shift register cells are quasi-static register cells, it is automatically ensured that when a "1" arrives via the data input DE of the channel selector KW the input of the AND gates A 1 to Ap also has a “1” pending on the input of these AND gates dedicated to the clock TM.
  • the game is repeated successively on the respective subsequent output channel V 4 to Vp until the addresses of the first p played tones are stored in one of the output channels and - as long as the memory state persists - ensures in the manner already described with reference to FIG. 2, that the tone frequency oscillation corresponding to the stored tone at the tone signal output AU 1 or AU 2 or 7-8 or AUp of the relevant output channel V 1 or V 2 or 7-8 or Vp to the respectively assigned amplitude former AF 1 to AFp is delivered.
  • Each of the output channels V 1 or ising or Vp of the switching system VM shown in FIG. 2 controls an amplitude former AF 1 or ising AFp with its output.
  • the structure of such an amplitude shaper is shown in FIG. 6.
  • the output is AU 1 or AU 2 or .... or AUp of the relevant output part V 1 to. V 2 or 7-8 or Vp at the input of a shaping circuit FS, each of which is combined with a counter Z.
  • a shaping circuit FS each of which is combined with a counter Z.
  • This patent application relates to a semiconductor circuit for the conversion of sequences of periodic AC signals with a signal input, a circuit part which effects the conversion and a signal output.
  • Characteristic of this semiconductor circuit is the measure that the signal input is connected to the one current-carrying connection of several identical transistors and each of these transistors is combined with another such transistor to form a pair of transistors by the other current-carrying connection of the first transistor of each transistor pair with the Corresponding current-carrying connection of the associated further transistor is connected and is also connected to the signal output of the circuit via one of n different resistor combinations, that the resistor combinations respectively assigned to the individual transistor pairs form a resistor network and that the first current-carrying electrodes of the second transistors of all of these Transistor pairs are at a common and different from the reference potential (ground) operating potential and that finally to act on the control electrodes of the transistors has an n count stages Transmitter and digital counter controlled by a clock generator with counting pulses is provided and the n transistor pairs are connected in different ways from case to case with the signal outputs of the digital counter.
  • the dual counter Z assigned to the individual amplitude shaper AF 1 to AFp is, as already explained in DE-A-29 16 765, designed as an up-down counter.
  • it has 7 counting stages in the form of seven flip-flop cells connected in series, e.g. B. toggle flip-flop cells, which are each provided with two inputs, ie a direct and an inverted input.
  • Each of the two inputs of the individual flip-flop cells forming the counter Z is connected to the gate of a respective MOS transistor of the enhancement type.
  • the drains of the two MOS transistors assigned to a counting stage in this way are connected to each other and each connected via a resistor to a dividing point of a voltage divider provided by 8 resistors connected in series in the example.
  • the source connections of the one of the two MOS transistors each assigned to a counter stage are connected to an average operating potential and the other transistor (assigned to the inverted input) with its source at the audio signal output AU 1 or 7-8 or AUp of the respective one Amplitude shaper AF 1 or .... or AFp assigned output channel V 1 or .... or Vp of the switching system VM.
  • Said voltage divider forms the signal output SG 1 or ?? or SG P of the relevant amplitude shaper at one end and is connected to the mean operating potential at the other end and thus to the source connections of the inputs of the individual which are acted upon in inverted fashion MOS transistors assigned to counting stages.
  • the signal outputs of the p provided amplitude formers AF 1 to AF P are each at an input of a mixing stage Mi, the output of which controls a loudspeaker LT, that is to say an electro-acoustic transducer, via an amplifier V. Details regarding the previously described parts of the amplitude shaping circuit shown in FIG. 6 need not be discussed further in connection with the present semiconductor circuit.
  • the count input of the up-down counter Z of the amplitude shaper is supplied by a system containing at least one oscillator for generating the counting clocks, the system itself being back-controlled by certain counts of the counter Z in question.
  • a system containing at least one oscillator for generating the counting clocks the system itself being back-controlled by certain counts of the counter Z in question.
  • two such oscillators OZ 1 and OZ 2 are provided, which are designed in a manner known per se such that they deliver square-wave oscillations with an adjustable frequency.
  • Each of these two oscillators OZ 1 and OZ 2 controls a frequency divider TL 1 and TL 2 , which in the example have three divider stages F 1 to F 3 and F 4 to F 6 in the form of flip-flop cells connected in series.
  • master-slave flip-flops are used for the individual divider stages, so that the oscillations supplied by the respective oscillator OZ 1 or OZ 2 directly to one input of the first flip-flop cell and the other input is fed via an inverter (not specifically designated).
  • These two oscillators OZ 1 and OZ 2 are common to all of the p amplitude shapers provided. They therefore control a total of p frequency dividers TL 1 and p frequency dividers TL 2 .
  • each divider stage F 1 to F 6 is connected to an input of one of the AND gates a 1 to a 6 . Accordingly, e.g. B. the AND gates a 1 to a 3 to the first divider TL, and the AND gates a 2 to the second divider TL 2 .
  • the outputs of all these AND gates a 1 to a 6 each go to an input of a common OR gate od.
  • the output of this OR gate od is present a further AND gate ug, which has two inputs, one of which is controlled by said OR gate od and the other by one output of a flip-flop cell FF.
  • the flip-flop LFF is acted upon at both inputs by an output of the logic circuit Lo.
  • This logic circuit Lo is in turn controlled by the up-down counter Z and by a start signal St, which is also provided for starting the RS flip-flop formed by the two NOR gates n 1 and n 2 .
  • the up-down counter Z has seven counting stages in the example. It controls the logic circuit Lo with the counter reading «0» as well as with its highest count and with the highest count as well as with two additional counts one of the three AND gates a 1 *, a 2 * and a 3 * (of course several such AND gates may also be provided), each having seven inputs and for the purpose of coding a specific count of the counter Z being acted upon by one of the two outputs Q and Q of each counter stage of Z.
  • the AND gate a1 * is assigned to a first count other than "0”
  • the AND gate a 2 * to a second - higher - count
  • the AND gate a 3 * to an even higher third count of Z, which in particular corresponds to the corresponds to the highest count of this counter Z.
  • a differentiation stage DS 2 is assigned to the third AND gate a 3 * , while the control by the other two AND gates a 1 * and a 2 * works without such a differentiation stage.
  • the AND gate a 1 * is connected to an input of the aforementioned NOR gate n 1 , which together with the NOR gate n 2 forms an RS flip-flop. For this purpose, its output is connected to an input of the NOR gate n 2 and the output of the NOR gate n 2 to an input of the NOR gate n 1 .
  • the first NOR gate n 1 also has a third input which is connected to a reset input of the circuit according to FIG. 6 which is controlled by reset signals. This reset input Re may also apply to the reset input of counter Z, so that when a reset pulse occurs it switches to the counter status "0" (if counter Z has not already been switched to "0" by the countdown phase).
  • a miket by a start signal St is input via a differentiating stage DS, on the one hand to the logic Lo and on the other hand to a second input of the NOR gate with n 1 cross-coupled NOR gate N2.
  • the output of the RS flip-flop formed by the NOR gates n 1 and n 2 is identical to the output of the NOR gate n 1 . It is connected to an input of the AND gates a 3 and a e acted upon by the two last divider stages F 3 and F e of the two dividers TL 1 and TL 2 .
  • a second RS flip-flop is connected through the two NOR gates n 3 to the output of the other NOR gate.
  • a second input of the NOR gate n 3 is at the output of the AND gate a1 *
  • a second input of the other NOR gate n 4 is at the output of the AND gate a 2 *
  • a third input of the NOR gate n 4 is at the reset input Re the circuit.
  • the output of the second RS flip-flop n 3 , n 4 is given by the output of the second of these NOR gates, that is to say by the output of the gate n 4 . It is connected to an input of the AND gates a 2 and a 5, respectively, which are acted upon by the two penultimate stages F 2 and F 4 of the two dividers TL 1 and TL 2 .
  • a third RS flip-flop is provided by the two NOR gates n 5 and n 6 , of which in turn one input is fed back to the output of the other gate. Another input of the gate n 5 is controlled by the output of the second AND gate a 2 * and another input of the other NOR gate n 6 by the output of the AND gate a 3 * via a differentiating stage DS 2 .
  • a third input of the NOR gate n 6 is at the reset input Re. Its output forms the output of the third RS flip-flop n 5 , n 6 . It is located at a respective input of the acted upon by the first divider stages F 1 and F 4 AND gates A 1 and A. 4
  • the output of the differentiating stage DS 2 which is controlled by the AND gate a 3 *, is also connected to an input of a further flip-flop cell AFF, the second input of which is connected to the reset input Re.
  • the output of the flip-flop AFF which receives the level “1” when a signal occurs at the output of the differentiating stage DS 2, is connected to a last input of the AND gates a 1 to a 3 controlled by the first divider TL 1 and via an inverter IR at a last input of the AND gates a 4 to a 6 controlled by the second divider TL 2 .
  • the same output of the flip-flop cell AFF is also connected to the input of the counter Z which effects the conversion of the counter Z from the up to the down-counting operation.
  • the other output of the flip-flop cell AFF can be used instead of the inverter IR to switch the third inputs of the To control AND gates a 4 to a 6 .
  • the inverter IR is then not required.
  • the design of the logic circuit Lo shown in FIG. 7 has two AND gates controlled by the two extreme levels of the up-down counter Z, the AND gate u 1 * being the highest, the AND gate u 2 * the lowest count, that is to say the Count «0 is assigned.
  • the AND gate u 1 * can be identical to the AND gate a 3 * , although in the case of the logic Lo the differentiation stage DZ 2 is not included.
  • the AND gates u 1 * and u 2 * each have seven inputs which, in the case of the AND gate u1 *, have those which indicate the count Outputs Q and in the case of the AND gate u 2 * are each connected to the outputs ⁇ of the counter Z which carry the inverted signals.
  • the AND gate u 2 * is connected via a differentiating stage DS 3 to the one input of an OR gate org 2 , the other input of which is controlled by a further AND gate ud 3 and the output of which is applied to the flip-flop LFF that this blocks the AND gate ug controlling the supply of counting pulses to counter Z.
  • the first-mentioned AND gate ud 2 is acted upon on the one hand by the AND gate u 1 * dedicated to the highest count of the counter Z (which is preferably identical to the AND gate a 3 * ) and on the other hand by a control input P / S supplied signal. In the presence of such a signal (or its absence) it is achieved that the sound amplitude maintains its constant amplitude as long as the signal continues even when the play key is released.
  • the other input of the flip-flop cell LFF is controlled by a further OR gate org 1 , which, in contrast to the OR gate org 1, ensures the supply of counting pulses to the counter Z via the AND gate ug.
  • the OR gate org 1 is also controlled by two AND gates ud 1 and ud 2 .
  • One input of the AND gate ud 2 is located at the control input P / S already mentioned, while the other input is acted upon by an input TLO.
  • a signal is given to the input TLO when the game button responsible for the current application of the considered amplitude shaper AF 1 to AFp is released in the manual M. The generation of this signal, which controls the input TLO, will be discussed after the pending further consideration of the channel selector KW.
  • the other AND gate ud 1 is connected with one input to the AND gate u 2 * assigned to the count “0” of the counter Z and with the other input to the input St carrying the start signal, through which the NOR gate n 2 is controlled. Since when the channel V 1 or V 2 or .... or Vp and the amplitude shaper AF 1 or AF 2 or .... or AF P controlled by it, the up-down counter Z changes to the count «0 is, the OR gate org 1 is activated by the start signal supplied via the start input St and thus the flip-flop LFF is brought to an operating state in which the downstream AND gate ug for those supplied by the output of the OR gate od Counting cycles is permeable.
  • the AND gate ud 3 acts, since this then also has the AND gate OR 2.
  • Gate ug throttles.
  • the AND gate ud 2 acts on the OR gate org 1 and thus on the flip-flop LFF as soon as it is at its one input at the same time by releasing the game key in the manual when the relevant key is released M arising and supplied via the input TLO and at the other input by a signal P / S (z. B. generated by a pedal).
  • the differentiating stages DS 1 , DS 2 and DS 3 can advantageously be designed in accordance with DE-A 28 45 379, since these trigger the immediate creation of a short defined pulse R due to a controlling pulse RZ.
  • the task of these differentiation stages DS 1 to DS 3 is to be seen in the present case in that an extremely short pulse of defined length is triggered when a control pulse of any length occurs.
  • the start signals St are advantageously the takeover signals UE 1 to UEp which are used to start the output part V 1 to V P assigned to the relevant amplitude former AF 1 to AF p and which are generated by the associated AND gate A 1 to Ap of the channel selector KW used, so that expediently the output of the relevant output part V 1 or .... or V P AND gate A 1 or .... or Ap to control the logic Lo in the downstream amplitude shaper AF 1 or .... or AFp is used for the delivery of the start signal St. As already stated, they are brought to the NOR gate n 1 as well as to the AND gate ud 1 in the logic circuit Lo via the differentiating stage DS 1 .
  • the flip-flop AFF Due to the start signal St, a “1” appears at the output of the NOR gate n 1 due to the specified conditions, which reaches one of the three inputs of the AND gate a 3 controlled by the third divider stage F 3 of the plate TL 1 . Furthermore, the flip-flop AFF is in a state in which the AND gate a. Is due to the initial state of the counter Z (be it because of a previous counting down to the count “0”, or because of a reset signal given via the reset input Re) 1 to a 3 can be loaded with a "1" by this flip-flop AFF. Finally, the two oscillators OZ 1 and OZ 2 are in continuous operation (they can be switched on, for example, by the start signal St).
  • the NOR gate n 1 would then have to be switched again to initiate the decay phase in such a way that a “1” appears at its output which, when the AND and Gate a 1 * corresponding count of Z disappears again, while at the same time the «1» appears at the output of n 4 .
  • the «1 at the output of the NOR gate n 4 disappears. Instead, the "1" appears at the output of the NOR gate n 6 and disappears again as soon as the counter status "0" now assigned to the AND gate a 3 * has been reached in the counter Z.
  • FIG. 8 In the end of the description of the channel selector KW according to FIG. 3, reference should be made to FIG. 8, in which the connection of the reference counter RZ already shown in FIG. 3 and the age counter AZ 1 to AZp (in the example, p is again 10) is shown .
  • the control AST of the age counters AZ 1 to AZp which is only indicated in FIG. 3, that is to say in the example case AZ 1 to AZ 10, is shown in FIG. 8.
  • Each age counter AZ 1 to AZp is assigned to one of the intended output channels V 1 to Vp of the switching system VM. In the exemplary embodiment shown in FIG. 8, its counting input is acted upon by the output of one AND gate UL 1 or UL 2 or ... or ULp. Furthermore, each of the age counters AZ 1 to AZp can be reset to the count “0” by an erase signal L 1 to Lp supplied by the respectively assigned amplitude shaper AF 1 to AFp upon its return to the initial state and by a general reset signal (not shown).
  • All age counters have the same number of counting stages, which also applies to the reference counter RZ assigned to the age counters AZ 1 to AZp.
  • a comparator K 1 * to Kp * is provided between the reference counter RZ and each of the intended age counters AZ 1 to AZp, which has already been mentioned and which, if the counter reading of the reference counter RZ is the same as the individual age counter AZ 1 resp. AZ 2 , etc., that is to say it outputs a «1.
  • the AND gates UL 1 to ULp allocated to the individual age counters AZ 1 to AZp deliver the counting clock for the respective age counter.
  • these AND gates UL 1 to ULp each have three inputs. One of these is acted upon by the OR gate OD * shown in FIG. 1 and controlled by the comparators K 1 to K P of the individual output channels V 1 to V P , which always supplies a “ 1 ” when at least one of the output channels V 1 to Vp is busy.
  • a circuit arrangement TLO 1 to TLOp is also assigned to each of the output channels V 1 to V P and thus to each of the age counters AZ 1 to AZ P.
  • B. can be configured according to FIG. 9 and which responds when the game button causing the application of the individual channel V 1 to Vp and thus the respectively assigned age counter AZ 1 to AZ P is released again. It supplies a signal which is provided for controlling the second input of the AND gate UL 1 or UL 2 etc. of the individual age counters AZ 1 ' AZ 2 etc. so that the age counter AZ 1 or AZ 2 etc. only then receives counting pulses when the key is released or the effect of the named circuit parts is blocked by a (common signal) P / S.
  • the third inputs of the individual AND gates UL 1 to ULp are acted upon together by counter clocks. These counting cycles can e.g. B. be supplied by the clock TG controlling the input shift register PSW.
  • the outputs of the AND gates UL 1 to UL P assigned to the individual age counters AZ 1 to AZp are each connected to an input of a common OR gate oe, the output of which supplies the counting clocks for the reference counter RZ.
  • each of the counting cycles supplied to one of the age counters AZ 1 to AZp also serves as a counting cycle for the reference counter RZ.
  • a comparator K 1 * to Kp * is provided between the reference counter RZ and each of the age counters AZ 1 to AZp.
  • the output of these comparators K 1 * to Kp * serves on the one hand to control one AND gate A, * to Ap *.
  • it is used by means of an inverter IR 1 or IR 2 or .... IR P to control the reset input of the age counter AZ 1 or AZ 2 etc., which for this purpose from the output of the associated inverter IR 1 to IR P via a Differentiation stage ds 1 or ds 2 or ... or dsp is subjected to a short reset pulse if the «1 on the associated comparator K 1 * or K 2 * etc. disappears.
  • the output of the individual inverters IR 1 to IR P acted upon by the comparators K 1 * to Kp * is also connected to an input of an AND gate assigned to all the comparators K 1 * to Kp * at 1 .
  • the reference counter RZ is designed as an up-down counter, which is switched on the basis of a signal supplied by the AND gate at 1 in the opposite counting direction and which in the absence of such a signal immediately tilts back into the up-counting direction.
  • the output of the AND gate at 1 is also at an input of a further AND gate at 2 , the output of which is at a further input of the OR gate OR oe controlled by the AND gates UL 1 to UL P and the other input of which is Clock pulses, e.g. B. is controlled by the clocks TM.
  • the response of the individual comparators K 1 * to Kp * means, as repeatedly emphasized, that there is equality between the count of the reference counter RZ and the count of an age counter. An exception is the initial state, since then not only one comparator, but all supply a "1", so that for this reason alone the reference counter RZ is initially kept at the count "0".
  • the OR gate OD * responds.
  • the first counting cycle for an age counter AZ 1 to AZ P is only due when one of the circuit parts TLO 1 to TLOp responds.
  • UL 1 or .. UL2 or ... or ULp is the counting clock which is acted upon by the signal TLO, that is to say by the respectively associated indicator TLO 1 to TLO P.
  • These counting clocks then arrive both at the counting input of the age counter belonging to the AND gate UL 1 to ULp, which is now permeable to the counting clocks, and via the OR gate oe at the counting input of the reference counter RZ, so that both counters builds up the same count.
  • the channel V 2 causing game button released so receives the age counter assigned to this channel, i.e. in the example the age counter AZ 2 ' now also the synchronous counting impulses, so that this age counter AZ 2 and in all other age counters belonging to a busy output channel and acted upon by one of the signals TLO each have an individual count builds up, the lower the later the age counter in question was acted on by the TLO signal assigned to it.
  • An erase pulse generated by the first responding output channel V 1 or by its amplitude shaper and applied to the reset input of the age counter AZ 1 ensures that the count of the age counter with the highest count is deleted.
  • the "1" at the output of the associated comparator K, * etc. disappears, so that the reference counter RZ corresponds to the count of the age counter which has the next highest count, e.g. B. the age counter AZ 2 is reset.
  • the age counter AZ 2 associated comparator that is, the comparator K 2 , with a “1” at its output, so that the countdown of the reference counter RZ is ended abruptly.
  • the process described is repeated with this, by resetting the reference counter to the count of this age counter AZ 5 , then by positive loading with the common counting clock synchronously with the new age counter AZ 5 is counted up; until the count of this counter is also cleared by a clear signal L 5 originating from the amplitude shaper AF S and the reference counter RZ is set to a new count, namely the next highest count.
  • the age counter-controlled comparator K 1 * or K 2 * etc. which has the highest count, has a “1” at its output, while all other of these comparators have an “O” at the output. If the AND gates A 1 * to Ap * which are provided with two inputs in FIG. 3 are each provided with a third input, this third input is controlled by a common overwrite signal US and that at the output of the individual AND gate A 1 * to Ap * supplied signal is not only used to control the associated OR gate from the series of OR gates OD 1 to ODp, but also uses this signal as a second erasure signal for the content of the memory parts S and S * of the associated output channel.
  • a circuit for generating the TLO signal is shown in FIG. 9.
  • the data input DE of the channel selector KW and the comparator K 1 are each connected to one input of an AND gate 1 and one input of a NOR gate 2.
  • the output of the AND gate 1 controls the.
  • Reset input R of an RS flip-flop 3 the output of the NOR gate the set input S of this flip-flop 3.
  • the Q output is at an input of a further AND gate TLO 1 ; the output of which provides the signal TLO.
  • the second input of the AND gate TLO 1 is controlled via an inverter through the input P / S.
  • V 1 ,... Vp the individual output channel
  • AF 1 ,... AFp a respective amplitude former
  • the AND gate u 2 * which responds at the count “0”, has its output connected to the one input of a further AND gate u 3 * , the other input of which is lonely with the control input of the up-down counter Z controlled by the flip-flop AFF (FIG. 6) for the duration of the operating state of the down-count.
  • the AND gate u 3 * only responds if the count “O” in the counter Z is reached when counting down.
  • the "1" that arises at the output of the AND gate u 3 * can, for. B. via an OR gate OT to the common reset input of the two memory parts S and S * (z. B. to the gate of the transfer transistors t 4 in an embodiment according to FIG. 5).
  • the OR gate OT is also from the output of the respective associated output channel (V 1 , ... Vp) and from the assigned age counter (AZ 1 , ... AZp) or from the comparator (K 1 , ... Kp * ) controlled AND gate A, * , ... Ap * forth, which, as already explained, responds to fully occupied output channels V 1 , ... Vp and due to an overwrite signal US.
  • the delete signal output at the output of the OR gate OT is in any case - e.g. B. by tilting the flip-flop AFF into the other operating state and by resetting the RS flip-flops n 1 , -n 6 to the initial state (the signal L then represents the reset signal Re indicated in FIG. 6) - is used to also spontaneously reset the amplitude shaper F 1 ' ... AFp assigned to the respective output channel V 1 , ... Vp to the initial state.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Acoustics & Sound (AREA)
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  • Electrophonic Musical Instruments (AREA)
EP80107529A 1979-12-04 1980-12-02 Digitale Halbleiterschaltung für eine elektronische Orgel Expired EP0030034B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19792948769 DE2948769A1 (de) 1979-12-04 1979-12-04 Digitale halbleiterschaltung fuer eine elektronische orgel
DE2948769 1979-12-04

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EP0030034A2 EP0030034A2 (de) 1981-06-10
EP0030034A3 EP0030034A3 (en) 1983-03-30
EP0030034B1 true EP0030034B1 (de) 1985-06-05

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EP (1) EP0030034B1 (ja)
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DE3025643A1 (de) * 1980-07-07 1982-02-04 Siemens AG, 1000 Berlin und 8000 München Digitale halbleiterschaltung fuer eine elektronische orgel
US4468998A (en) * 1982-08-25 1984-09-04 Baggi Denis L Harmony machine
JP2714954B2 (ja) * 1988-05-25 1998-02-16 ローランド株式会社 発音制御装置
US5455141A (en) * 1992-05-29 1995-10-03 Eastman Kodak Company Photographic elements containing blocked dye moieties
EP2043088A1 (en) * 2007-09-28 2009-04-01 Yamaha Corporation Music performance system for music session and component musical instruments

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US3696201A (en) * 1970-11-12 1972-10-03 Wurlitzer Co Digital organ system
US4041826A (en) * 1974-08-07 1977-08-16 Nippon Gakki Seizo Kabushiki Kaisha Electronic musical instrument
JPS5245322A (en) * 1975-08-06 1977-04-09 Kawai Musical Instr Mfg Co Ltd Circuit for selecting key signals in electronic musical instrument
JPS6034759B2 (ja) * 1976-07-02 1985-08-10 株式会社河合楽器製作所 電子楽器の鍵盤回路
JPS5494316A (en) * 1978-01-10 1979-07-26 Nippon Gakki Seizo Kk Electronic musical instrument
JPS54151435A (en) * 1978-05-19 1979-11-28 Nippon Gakki Seizo Kk Electronic musical instrument

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US4357853A (en) 1982-11-09
EP0030034A3 (en) 1983-03-30
EP0030034A2 (de) 1981-06-10
DE2948769A1 (de) 1981-06-11

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