EP0030034B1 - Digital semiconductor circuit for an electronic organ - Google Patents

Description

The invention relates to a digital semiconductor circuit for an electronic organ with a number of control inputs applied to the manual corresponding to the number of play keys of the manual of the organ and with a number of sound signal inputs applied by an oscillator system with periodic electrical oscillations, in each of which one control input each Game key of the manual and one audio signal input each is assigned a fixed audio frequency, in which an audio signal output is also provided for the application of an electro-acoustic transducer and in which the control signals serving for the control inputs finally correspond to the logic levels.

For example, in known digital semiconductor circuits of this type, the individual control inputs are acted on by each of these control inputs being able to be applied via a switch to a common first operating potential assigned to the level “1, and when the individual game button is actuated, the associated switch is closed as a result of the actuation. Control inputs whose game buttons are pressed have the level «1 •, control inputs whose game buttons have not been pressed have the level« 0 »accordingly. Furthermore, in known electronic organs, a generator is used to generate the sound frequencies, which - starting from an oscillator delivering a square wave with the highest frequency corresponding to the two logic levels - delivers the individual tone vibrations by frequency division at least to the highest octave of the organ and to one input each provides an AND gate with two inputs, the second input of which is acted upon by the associated control input. The entirety of these AND gates is then provided to act on the audio signal outputs.

It is now possible to assign an amplitude former to each game button and thus to each input of the digital semiconductor circuit of the electronic organ. However, the effort involved is undesirably high, especially when the semiconductor circuit is implemented monolithically. On the other hand, for musical reasons it is impossible to provide only one signal output from the digital circuit of the organ and, accordingly, only a single amplitude shaper. This means that the digital semiconductor circuit of the organ is to be provided with several, in particular expediently with ten, signal outputs, which are then each connected to the input of an amplitude-shaping circuit. The entirety of the amplitude formers is then connected to a common output to act on the electro-acoustic transducer, in particular a loudspeaker.

For this purpose, it is provided according to the invention that the individual control inputs are each assigned to a cell of a clock-controlled shift register and operated as a parallel series converter, and that both the signal output of the shift register and the clock pulses provided for its operation serve to control a switching system which serve the entirety the intended sound signal inputs and the sound signal outputs,. the number of which is lower than the number of control inputs, that each of the sound signal outputs is assigned an amplitude shaper and that finally the outputs of the amplitude shifters are connected to an electro-acoustic transducer.

• 1. Die p Tonsignalausgänge der Vermittlungsanlage sind nummeriert, d. h., entsprechend einer Hierarchie geschaltet.
• 2. Die Gesamtheit der n Steuereingänge wird periodisch abgefragt, d. h., das Schieberegister in die Vermittlungsanlage geleert. Dabei ist angestrebt, daß zwischen zwei aufeinanderfolgenden Abfragevorgängen die jeweils zuerst gedrückte Spieltaste bzw. der ihr zugeordnete Steuereingang auf den ersten Tonsignalausgang, die als nächste gedrückte Spieltaste auf den zweiten Tonsignaleingang entsprechend der unter 1. genannten Hierarchie geschaltet wird. Wie bereits bemerkt, wird bevorzugt die Zahl p der Tonsignalausgänge auf p = 10 (entsprechend der Fingerzahl) festgelegt. Außerdem wird der zeitliche Abstand aufeinanderfolgender Abfragezyklen so kurz bemessen, daß er höchstens der zum Spielen eines Akkords durch den raschesten Spieler benötigten Zeitspanne entspricht. Demzufolge ist im allgemeinen damit zu rechnen, daß pro Abfragezyklus höchstens eine weitere Information aus dem Manual in das als Pärallel-Serienwandler betriebene Schieberegister eingeht.

In a preferred embodiment, a total of 5 octaves and a key, that is 61 game keys and accordingly 61 control inputs are provided in the digital semiconductor circuit according to the invention in the manual of the organ. In the general case, a different number, eg., For the number n of the game keys and thus for the number n of the control inputs. B. 75 may be provided. The number m of the sound signal inputs is z. B. fixed to m = 12, while the number p of the sound signal outputs and thus the number of amplitude shapers provided in the circuit is preferably p = 10. The core of the invention is the switching system, the aim of further embodiments of the invention being to design it according to at least one of the following aspects:

• 1. The p sound signal outputs of the switching system are numbered, ie switched according to a hierarchy.
• 2. The entirety of the n control inputs is queried periodically, ie the shift register is emptied into the switching system. The aim is that between two successive interrogation processes, the game button pressed first or the control input assigned to it is switched to the first audio signal output, and the game button pressed next is switched to the second audio signal input in accordance with the hierarchy mentioned under 1. As already noted, the number p of the audio signal outputs is preferably set to p = 10 (corresponding to the number of fingers). In addition, the time interval between successive query cycles is dimensioned so short that it corresponds at most to the time required for the fastest player to play a chord. Accordingly, it is generally to be expected that at most one additional piece of information from the manual will enter the shift register operated as a parallel-to-serial converter per polling cycle.

In the event that, on the other hand, between two successive interrogation processes, a number of control inputs exceeding the number p is applied, that is, for. B. more than ten notes are played, the excess should Information taking into account the hierarchy indicated under 1. and 2. are ignored.

3. Once a sound signal output or channel is occupied, the aim is to only release it again when the sound, and thus the electrical information causing the sound, in the amplitude shaper affected by the sound signal output has decayed after the play key causing the assignment has been released. On the other hand, a reverberation effect is provided so that the sound played is not suddenly suppressed when the play button is released.

If a game button is released when the tone signal outputs are fully occupied and another game button is struck in its place, the new tone is to be generated via the tone signal output that has been released by releasing the other game button. If several game buttons are released at the same time when the audio signal outputs are fully occupied and a new game button is pressed, the information associated with the new game button and the audio signal that it calls up should be applied to the audio signal outputs that this frees up, in which the tone that was played last and still remains in the reverberation effect faded most. If a released game button is finally struck again immediately, it is advisable to reassign the old sound signal output to the switching system.

The invention will now be described with reference to FIGS. 1 to 10. In Fig. 1 the essential parts of the invention are shown in the block diagram, while the remaining figures deal with details of the switching system and the amplitude shaping.

In the manner already indicated, the n control inputs E ₁ , E2,... E _n , or in short E _v , of the semiconductor digital circuit according to the invention are now acted upon by the individual game keys of the manual M. These n control inputs E _v form the information input for each register cell of a clock-controlled shift register PSW, which is operated as a parallel series converter and is supplied by a clock generator TG with the shift clocks required for pushing out the information supplied by the manual M during the individual query cycles. The shift register PSW preferably has n register cells, so that each control input E _{v has} a register cell and each register cell has a control input E _v control input E _{v of} the shift register PSW.

The data output DA of the shift register PSW is connected to the data input DE of a so-called channel selector KW, which at the same time forms an information input of the switching system VM. As a further information input, the switching system contains the count input of a sound address counter TAZ, which is designed as a digital counter on a binary basis and is described in more detail with regard to its design and control.

In addition to the channel selector KW and the sound address counter TAZ, the switching system VM p contains mutually identical output parts, that is to say output channels V, to Vp, which are controlled on the one hand by the channel selector KW and on the other hand by the sound address counter TAZ. In addition, the switching system has m audio signal inputs, which are acted upon by an audio frequency generator TOS.

The tone frequency generator TOS is designed in the usual way and has a number of tone frequency outputs, each of which is assigned to a tone frequency. The tone frequency generator TOS usually has twelve tone frequency outputs, each of which provides a periodic square wave with a frequency that is assigned to a tone of the highest octave of the range of the organ. Such a tone frequency generator has as its core a rectangular oscillator which provides a square wave with a sufficiently high frequency to be able to derive square waves with the frequency corresponding to the tones of the highest octave with the help of frequency dividers. These are then made available at each of the m = 12 audio frequency outputs of the audio frequency generator TOS.

The m audio frequency outputs of the audio frequency generator TOS have m audio signal inputs TSE of the switching system VM, of which only one is shown in FIG. 1. In the case of m = 12 one has twelve such inputs TSE, each of which is assigned to a tone frequency of the highest octave.

The individual sound signal input TSE of the switching system VM is connected to an input (designated in the same way) of each of the mutually identical output channels V, or V ₂ ,... Or Vp. Each of these output channels V, to Vp is provided with means which allow a reduction of the square waves delivered by the tone frequency generator TOS to the frequencies of the corresponding tones in the lower octaves. In addition, these output channels V ₁ to Vp are each provided with an audio signal output AU ₁ , AU ₂ , ... AUp, from which the audio signals selected via the 2 Manual M are applied to the downstream amplitude formers AF, or AF ₂ , ... or AF _P violate. The output of the individual amplitude shaper AF ₁ or AF ₂ , ... or AFp is z. B. in the manner shown in FIG. 6 for controlling a common electro-acoustic transducer, that is, a loudspeaker system.

It should also be noted that each of the mutually identical output channels V ₁ or V ₂ ,... Or Vp has a further output B ₁ . or B ₂ , ... or Bp, via which there is a reaction on the channel selector KW on the one hand, and on the other hand an additional control of the respectively associated amplitude shaper AF ₁ or AF ₂ , ... or AFp.

The tone address counter TAZ consists of two parts. The first part consists of four flip-flop cells connected in series in a known manner, e.g. B. from toggle flip-flop cells, each representing a binary counter. The counting stages are switched in such a way that the first part of the counter counts up to " ₁₂ ", so that when the thirteenth counting pulse arrives, it is already switched back to the initial state "0" simultaneously with the arrival of the thirteenth counting pulse (and only every thirteenth counting pulse) a counting pulse is given to the second part of the sound address counter TAZ. The second part of the sound address counter TAZ consists of three flip-flop cells connected in series and thus of three counting stages. They are switched in such a way that the highest count corresponds to the total number of octaves provided and is therefore preferably "6 or" 7.

The easiest way to achieve the above-mentioned behavior of the tone address counter TAZ is to include those outputs of the four flip-flop cells forming the first counter portion, which therefore show a " ₁ " at 12 at the desired highest count, with one input of an AND gate connects four inputs so that when the highest count is reached, a «1» also appears at the output of the AND gate. This is then fed to the reset input of the first part of the sound address counter TAZ and to the counting input of the second part of the sound address counter. As can be seen, the individual counting states of the first part of the counter TAZ are dedicated to the individual tones within the individual octaves and the individual counting states of the second part are each dedicated to an octave in the range of the organ.

The parallel series valve ^g isfer PSW z. B. also consist of a common shift clock T controlled master-slave flip = flop cells or better so-called quasi-static shift register cells. As already explained, the total number of register cells corresponds to the number of game keys in the manual M. Each register cell has its own information input, which is connected via a clock-controlled transfer gate to the control input E _{v of} the digital semiconductor circuit, each of which is supplied with logic information from the manual M. which is assigned to the relevant register cell by PSW. The entirety of the transfer gates mentioned is controlled by a takeover clock UE, which is also provided by the clock generator TG which supplies the shift clocks T and thus the counting clocks for the counter TAZ. With regard to an advantageous embodiment of the shift register PSW z. B. to DE-A-29 24 526, with regard to an advantageous embodiment of the clock generator TG to DE-A-27 13 319, 28 37 855, 28 37 882 and 28 45 379.

If any game key of the manual M is now pressed, a “1” appears at the control input E _{v of} the digital semiconductor circuit assigned to it, which is then written into the register cell of the shift register PSW assigned to this control input due to the following takeover clock UE. The now following shift clocks T ensure that the shift register PSW is emptied until the next takeover clock pulse UE. The information stored in the individual register cells successively passes the information output D of the shift register PSW in order to be entered in the channel selector to be described in more detail. The shift clocks T to be used for this purpose are also evaluated via the address counter TAZ in a manner to be described.

For this purpose, the structure of the individual output parts V ₁ or V ₂ ... Or Vp, which can be seen in FIG. 2, will now be discussed in more detail.

A read-write memory forms an essential part of each of these output parts of the switching system VM. Like the address counter TAZ, this memory also consists of two parts, namely a part S and a part S ^* . The first part S receives its information on the basis of the part of the address counter TAZ assigned to the individual sound names, the second storage part S ^* , on the other hand, is supplied with information to be stored due to the effect of the second part of the sound address counter TAZ assigned to the octaves.

The information read out from the first memory part S is sent via a first decoder D to twelve AND gates U ₁ to U _{12 '} which are simultaneously acted upon by the entirety of the audio frequency inputs TSE, while the information obtained from the second memory part S ^{* is used} to act on a second decoder D ^*. are provided. In addition, the information provided from the two memory parts is used to control a NOR gate NR, which in turn controls the smoke input B ₁ or B ₂ ... or Bp of the output part V ₁ or V _2, etc., already mentioned when looking at FIG. 1 . forms.

Immediately after each takeover clock UE, which inputs the information into the input shift register PSW, the serial readout of the respectively recorded information from this shift register and the structure of the information relating to the two memory parts S and S ^* commence in a manner to be described. Each of the two memory parts is expediently made up of discrete memory cells, in particular of discrete quasi-static register cells corresponding to the input shift register PSW, the clock pulses TM for the input shift register PSW or the counting clocks for the sound address counter TAZ as shift clocks for the construction of the memory content of both memory parts S and S ^* are used, as will be explained in more detail with reference to FIG. 3.

For example, the data output DA of the input shift register PSW can be connected to the one input of an AND gate for this purpose place, whose other input is controlled by the shift clocks T or by secondary pulses derived therefrom. The output of this AND gate only delivers a “1” if a “1” passes through the data output DA of the input shift register PSW. The bits appearing at the output of the AND gate and assigned to the individual shift clock pulses arrive at the information input of the first memory part S and at the information input of the second memory part S ^*. The effect of clock sequences derived from the shift clocks or in some other way ensures that the “1 in the first memory part S in the memory cell assigned to the position corresponding to the sound being played within the octave and in the second memory part S ^* in that of the sound played containing the memory cell associated with the octave. The respective stored contents of the two memory parts are erased by a common residual pulse, which is advantageously identical to the takeover pulses UE regulating the information input into the input shift register. Further details regarding the information input into the two memory parts S and S ^{* of} the individual output parts V ₁ ... Vp are brought up in connection with FIG. 3.

A decoder D or D ^{* is} assigned to each of the two memory parts S and S ^* .

The first memory part S, which is used to hold the 4-bit word forming the sound address within the individual octave, accordingly consists of four individual shift register cells, which are evaluated in parallel via the decoder D - a “one-out-of-twelve decoder”. Accordingly, the first decoder D, which has twelve signal outputs and has twelve signal outputs corresponding to the 12 tone names, c, cis, d, dis, is assigned one AND gate U ₁ or U ₂ ,... Or U _{12 for} each signal output. Each of these AND gates has two inputs. The second input is each connected to one of the twelve sound signal inputs TSE in a manner already indicated, which in turn are acted upon by one of the twelve sound frequency outputs of the sound frequency generator TOS and thus each with one of the sound frequencies of the highest octave. The output of each of the AND gates U ₁ to U ₁₂ is connected to an output of a common OR gate O.

With regard to the effect of the part of FIG. 2 described so far, it should be noted that, due to the respective content of the first memory part S, one of the 12 outputs of the decoder D receives a "1", while the others retain the "0". Accordingly, the tone frequency from the highest octave supplied by the tone generator TOS via the tone signal input TSE assigned to the relevant decoder output appears at the output of the OR gate 0 mentioned.

The second memory part S ^* is acted upon by a 3-bit word forming the address of the octave selected in each case by the actuated play key and likewise controls a decoder D ^* in parallel operation ^. This is designed as a “1-out-of-six decoder” and accordingly has six signal outputs, of which only one receives the level “1” due to the information present in the memory section S ^* .

In general, with regard to the configuration of the second memory section S ^*, with any number q of the octaves provided in the manual, it can be determined that the second memory section S ^* then has q memory cells, that is to say shift register cells, which act as a «one-out q decoder »D * are formed, and then this decoder D ^* q controls the AND gates U ₁ ^* to U _o ^* .

In the example shown in FIG. 2, a total of 6 octaves are provided in the manual M, so that the memory section S ^{* has} only three information outputs leading to the decoder D ^* and the latter is designed as a “one-of-six” decoder.

Each of the q outputs of the second decoder D ^* is assigned one of q AND gates U ₁ ^* , U ₂ ^* , ... U _o ^{* in} that the decoder output in question is connected to one of the two inputs of the AND gate U _{1 assigned to it} ^{* is connected} to U _o ^* , while the other input of the relevant AND gate is acted upon via a frequency divider TT controlled by the first OR gate 0 controlled by the first decoder D and the tone generator TAZ. The entirety of the ^* acted upon by the second decoder D AND gate U ₁ to U ^* _o ^* lies with their signal outputs at a respective input of a second OR gate O ^*, the signal output of the tone signal output AU ₁ and AU _2, ... or AU _P forms when the considered output part of the switching system VM is its first output part V ₁ or its second output part V ₂ ... or its last output part Vp.

The frequency divider TT controlled by the first OR gate 0 is henceforth referred to as a tone divider, since it has the task of frequency dividing the tone signals belonging to the tones of the highest octave and supplied by the tone generator TOS, for the output AU ₁ or: AU ₂ . .. or AUp to generate certain tone vibrations.

Each of the ^* is controlled by the second decoder D AND gate U ₁ to U _o ^* - that in the example U ₁ ^* to U ₆ ^* - is controlled at its second input via the first OR gate 0 and in the following way: The The output of the first OR gate 0 is not only at the input of the sound divider TT but also at the second input of the first of the AND gates U _i ^{* mentioned.} The signal output of the first divider stage of the sound divider TT is at the second input of the second AND gate U ₂ ^* , the signal output of the second divider stage at the second input of the third AND gate U ₃ ^* etc., so that the (q-1) th 2, the fifth divider output at the second input of the last (= q-th) of this AND gate, that is to say at the second input in the example of the AND gate U ₆ ^* . In this way, each of these ^* is controlled by the second decoder D AND gate U ₁ is U ^* to ^* _o assigned to each one of the foreseen in the Manual M octaves.

Accordingly, due to the respective contents of the first memory part S, the tone selected in each case is supplied as the tone of the highest octave to the AND gate U ₁ ^* and to the tone divider TT via the decoder D. The addressing of the octave selected via the manual M stored in the second memory section S ^* then activates only one of the AND gates U ₁ ^{* -} Uq ^* , that is to say in the example case U ₁ ^{* -} U ₆ ^* , so that when U ₁ ^* the selected tone of the highest octave, when activating U ₂ ^* the selected tone of the second highest octave and when activating U _o ^* the selected tone from the lowest octave to the second OR gate 0 ^* and thus to the signal output AU of the relevant output channel - if this has been selected by a corresponding signal via its control input UE ₁ or UE ₂ or .... UE _P from the channel selector KW.

For the feedback control on the channel selector KW and for influencing the amplitude shaper AF ₁ to AFp downstream of the respective output part V ₁ -Vp, as already indicated in FIG. 1, a control input B ₁ or B ₂ or ... or Bp signals required. In order to obtain this, each -the ^* controlled by the two memory parts S and S input of the decoder D and D ^* is connected to one input of a NOR gate NR, the only a signal via the return control input B _{1 'or} B ₂ etc. gives up when the two memory parts S and S ^* of the output channel V ₁ and V ₂ etc. are empty.

A comparison is also provided between the signal input and the signal output of each of the memory cells of the two memory parts of the individual output channel V ₁ to Vp. This can e.g. B. via an equivalence gate E ₁ or E2 or .... or .... Ep (in the example case E ₁₀ ), the outputs of which are each at an input of an AND gate UL with p inputs at one input of an AND -Gatters UL with p inputs (i.e. in the example with 10 inputs) happen. The entirety of these equivalence gates with the AND gate forms a comparator K ₁ or K ₂ , etc. A “1” at the output of the AND gate UL indicates that the sound address stored in the relevant output channel V ₁ to Vp is equal to the counter reading of the sound address counter TAZ.

Instead of the configuration of the individual comparators K ₁ to K _P just described by equivalence gates, the gates E ₁ to Ep can all also be exclusive OR gates. However, the AND gate UL must then be replaced by a corresponding NOR gate.

The task of the comparators K ₁ to Kp is, as the further considerations will show, diverse. One of the tasks is to indicate that the relevant output channel V ₁ to Vp is occupied. A common task of these comparators is to control the KW channel selector. This takes place with the intermediation of an OR gate OD ^* , as can be seen from FIG. 3.

The various functions that are to be performed by the switching system VM are primarily controlled via the channel selector KW. The block diagram of a preferred embodiment of the channel selector KW is shown in FIG. 3.

The sound address counter TAZ and the address memory parts S, S ^{* of} the individual output parts V ₁ or V ₂ or .... or V _P (in the example case) are of the embodiment of the switching circuit and the overall circuit shown in FIG. 2 p = 10, as already indicated above) and the comparators K ₁ to Kp given by the equivalence gates E ₁ to E ₇ and the OR gates OR controlled by them, since on the one hand they are directly exposed to the control effect by the channel selector KW and in turn have repercussions on the channel selector.

Each of the intended output channels V ₁ to Vp is assigned an AND gate A ₁ or A ₂ or ... or Ap (in the example case A ₁ to A ₁₀ ) in the channel selector KW. Each of these AND gates A ₁ to Ap is controlled via two inputs, of which one at the data input DE of the channel selector controlled by the input shift register PSW and the other at the output of an OR gate OD ₁ or OD ₂ or respectively. .. or OD _P lies. The signal output of each of these AND gates A ₁ to Ap forms the control output UE ₁ or UE ₂ or UEp, which is used for additional control of the associated output part V ₁ or V ₂ or ... or V _{P of} the switching system VM each associated address memory S and S ^* is used, which will be discussed in more detail.

The OR gates OD ₁ or OD ₂ or ... or OD _{P which} control the individual AND gates A ₁ to Ap just mentioned have a first input, each of which is controlled by the output of a further AND gate UG ₁ or UG ₂ or ... or UGp is applied immediately. A second signal input of each of these OR gates OD ₁ to ODp is controlled by the signal output of a further AND gate A ^* ₁ to A * p.

The AND gates UG ₁ to UG _P mentioned in connection with the control of the OR gates OD ₁ to ODp have three inputs, with the exception of the AND gate UG ₁ assigned to the first output part or channel V ₁ , while that to the first channel V ₁ assigned AND gate has only two inputs. One of the inputs of all of these AND gates UG ₁ to UGp is through the control output B ₁ or B ₂ or Bp of the relevant output part or channel V ₁ or V ₂ or Vp (given by NOR gate NR) controlled while another input of each of these AND gates via an inverter IV is controlled by a common NOR gate NO. One input each of the other AND gates A ₁ ^* to Ap ^* already mentioned is located directly at the output of this NOR gate NO, the inputs of which act on the switching system VM via one of the total output parts V ₁ to Vp via its control output B ₁ to Bp are.

The first output part V ₁ associated AND gate UG ₁ is therefore fully controlled by the control output B ₁ and by the NOR gates NO. The remaining AND gates from the group of AND gates UG ₁ to UGp have, as just stated, three inputs, two of which are controlled in an analogous manner to the two inputs of the first of these AND gates UG ₁ . Accordingly, there is one input of each of these AND gates UG ₂ to UGp at the output of NOR gate NO via inverter IV and a second input at control output B ₂ or B ₃ or ... or Bp of the respective associated output part V ₂ or V ₃ or ... or Vp of the switching system VM. The third input of these AND gates UG ₂ to UGp is via the output of a logic cell L ₁₂ or L23 or ... or L _{(P-2), (p-1)} or _. L _{(p-1), p} controlled.

The logic cell L ₁₂ , which is provided for controlling the third input of the second AND gate UG ₂ from the series of AND gates UG ₁ to UG _P , consists only of an inverter, the input of which is through the control output B _{1 of} the first output part V , the switching system VM is controlled (which is also at the one input of the AND gate UG ₁ ) and its output is connected on the one hand to the third input of the AND gate UG ₂ (assigned to the second output part V ₂ ) and on the other hand at the input of next logic cell L _{23, which} is provided for loading the following AND gate UG ₃ .

The remaining logic cells L ₂₃ to ^L (p-1), p are identical to one another and each consist of an inverter L _23a or L _34a or ... or L _{(p-1), pa} and a NOR gate with two Inputs, the output of which forms the signal output of the logic cell concerned and which is designated L _23b , L _34b , ... L _{(p-1) pb} (see _FIG . 4). In terms of circuitry, the input of inverter a of the relevant logic cell L ₂₃ or L ₃₄ or ... or L _(p-1). p with the output of the preceding logic cell L ₁₂ or L ₂₃ or ... or L (p.

2). (p-1) connected, while its output is at the one input of the respectively associated NOR gate b. The other input of the NOR gate b of the relevant logic cell L ₂₃ to L _{(p-1), p} is from the control output B ₁ or B ₂ or ... or Bp of that output part V ₃ or V ₄ or ... or Vp controlled to which the relevant AND gate from the series of AND gates UG ₁ to UG _{P is} assigned. The construction and connection of the logic cells is shown in FIG. 4 using the first three of these logic cells, namely logic cells L ₁₂ , L ₂₃ and L ₃₄ .

In the channel selector (or output part selector) KW shown in FIG. 3, the output of the NOR gate NO not only causes the AND gates UG ₁ to UGp that have just been discussed, but also another group A ₁ ^* to Ap ^* controlled by AND gates, which are also each assigned to one of the output channels V ₁ to Vp of the switching system VM. Each of these AND gates A ₁ ^* to Ap ^* z. B. has two inputs, one of which is directly connected to the output of the NOR gate NO without the interposition of an inverter or another component, while the other is located at the output of a comparator K ₁ ^* to Kp ^* . The structure of the comparators K ₁ ^* to Kp ^* corresponds to that of the individual comparators K ₁ to Kp. On the one hand, they are loaded by a common reference counter RZ and on the other hand by a so-called age counter AZ ₁ or AZ ₂ etc. and speak at the same time as the count each of the p age counters AZ ₁ to AZp provided and each assigned to one of the p output channels V ₁ to Vp with the respective count of the reference counter RZ.

The mode of operation of the channel selector KW shown in FIGS. 3 and 4 will now be described. It is useful to go into the formation of the individual memory parts S and S ^* in the individual output channels V ₁ to Vp. It is recommended that the individual memory cells of these memory parts are formed from quasi-static shift register cells. In contrast to a write register, however, no series connection of the memory cells is provided here, but each memory cell is provided for itself both on the input side and on the output side. All that is common is the loading via the manual M and the clock supply.

A total of seven memory cells S ₁ to S _4. And S ₁ ^* to S ₃ ^{* are} assigned to each of the output parts V ₁ to Vp, the four cells S ₁ to S _{4 being represented} by the first part of the sound address counter TAZ and the three cells S ₁ ^* to S ₃ ^* are controlled by the second part of the sound address counter TAZ. Accordingly, the memory cells of the first memory part S are intended for receiving the designation of the particular sound being played within the individual octave and the memory cells of the second memory part for recording the designation of the octave in which the respective played or to be played sound is located. Accordingly, the signal outputs of the first storage part S forming memory cells S ₁ to S are still ₄ to S ₃ are provided for acting on the first decoder D and the outputs of the second storage part S ^* forming memory cells S ₁ ^* for control of the second decoder D ^*. 5, which will be discussed before the further description of the mode of operation of a channel selector KW according to FIG. 3, only the first three memory cells S ₁ to S _{3 of} the first memory part S are shown. In structure and in connection, the remaining memory cells S ₄ or S ₁ * to S ₃ ^* correspond in full to the memory cells shown in FIG.

Each of the memory cells of the two memory parts S and S ^* in each output channel V ₁ to Vp contains four transfer transistors t ₁ , t ₂ , t ₃ and t ₄ , each of which is provided by an enhancement-type MOS transistor. It also contains an inverter 1 and a NOR gate N. In addition, a so-called three-phase clock generator, that is to say a clock generator TG, which is capable of delivering three periodic pulse trains TM, TS and TSS having the same frequency, is required. It is essential for the three pulse sequences that the individual pulses TS are arranged without overlap between two pulses of the sequence TM, so that a space is provided between each of the adjacent pulses TM and TS. In addition, the falling edges of the pulses from the sequence TSS coincide with the falling edge of one pulse each from the sequence TS while the pulses TSS are slightly delayed with respect to the pulses TS with respect to the rising edge. Since the input shift register PSW is also expediently constructed using quasi-static register cells, that is to say with cells corresponding to FIG. 5, the clocks TM, TS and TSS are also required here. Finally, the individual counter stages of the sound address counter TAZ and other counters used in the circuit, in particular also the reference counter RZ and the age counter AZ ₁ to AZp, are built up by means of master-slave flip-flops (in particular by means of one toggle flip-flop each) , for which the Impulse TM and TS are also required.

As can be seen from FIG. ₁ , the data input of each of the memory cells forming the memory parts S and S ^{* is} formed by the source terminal of the transfer transistor t ₁ , which is accordingly connected to the counting output Q of the counter stage of the sound address counter TAZ assigned to it. The gates of the input transfer transistors t _{1 of} all of these memory cells S ₁ to S ₄ and S ₁ ^* to S ₄ ^* are together at the output of the channel selector outputs UE ₁ and UE ₂ assigned to the respective output channel V ₁ to Vp and controlling them or ... or UEp-forming AND gates A ₁ or A ₂ or ... or Ap. If the memory cells shown in FIG. 5 are used, the AND gates A ₁ to Ap must be equipped with three signal inputs each. Two of them are acted on in the manner shown in FIG. 3, while the third is controlled by the clocks TM controlling the memory cells S _{1 '} S ₂ etc.

The drain of the transistor t _{1 of} each of these memory cells S _{1 '} S ₂ etc. lies on the one hand at the input of an inverter I, on the other hand on one current-carrying electrode of two transfer transistors t3 and t4. The output of the inverter is connected via a transfer transistor t2 to the one input of a NOR gate N, the second input of which is controlled by a general reset signal Re and the output of which forms the output of the relevant memory cell. The gates of the transfer transistors t2 of the memory cells are controlled together by the clock TS.

The transfer transistors t3 bridge with their source-drain path the series circuit of inverter I, transfer transistor t2 and NOR gate N. Their gate is controlled by the clock pulses TSS. The transfer transistor t4 lies with its source-drain path between the reference potential (ground) and the input of the inverter I. Its gate is acted upon by pulses L generated in a manner to be described. The output of the NOR gates N of each of the memory cells S _{1 '} S ₂ etc. is on the one hand connected to the input of one of the two decoders D or D ^{* assigned} to it. On the other hand, each of the seven memory cells is assigned one of the comparison gates E ₁ to E _{7 of} the comparator K ₁ or K ₂ etc. For this purpose, one input of the relevant equivalence gate E ₁ or E2 or ... or E _{7 of} the comparator K _{1 '} K ₂ ... Kp in question is connected to the source connection of the input transfer transistor t ₁ and the other input to the Output · of the NOR gate N of the memory cell concerned. It should be noted that the erase pulses L controlling the gate of the transistors t ₄ are given by pulses selected from the sequence TM. Their generation is still being discussed.

The “1” that arrives at the source of the input transfer transistor t ₁ assigned to the individual memory cells in the memory parts S and S ^{* of} the individual output channel V ₁ to Vp is obtained in the respective memory cell due to the two clock sequences TS and TSS until an erase pulse L erases the "1" via the erase transistor t4 and the memory cell is thus again available for writing a "1". Since the erase pulse L reaches all the erase transistors t4 of the memory cells S _{1 '} S ₂ , etc. associated with the respective output channel K ₁ to Kp etc., the two memory parts S and S ^{* of} the respective output channel are erased simultaneously, so that the channel is re-exposed through the sound address counter TAZ. This is indicated by the "1" on the control output S _{1 '} S ₂ etc. of the relevant channel V ₁ , V ₂ , ...

• 1. Jedesmal wenn durch die Ausgänge der Zählstufen im Tonadressenzähler TAZ der Zählstand erreicht wird, der in den beiden Speicherteilen S und S^* jedes Ausgangskanals V₁ bis Vp eingespeichert ist, so erscheint am Ausgang des dem betreffenden Ausgangskanals V₁, V₂, usw. zugeteilten Komparators K_1' K₂ usw. eine « 1 ». Dies gilt auch, wenn der Zählstand von TAZ gleich « 0 ist und die betreffenden Speicherteile S und S^* leer sind. In allen anderen Fällen liegt an den Ausgängen der einzelnen Komparatoren K₁ bis Kp eine « 0 ».

In summary it can be stated:

• 1.Every time when the outputs of the counter stages in the sound address counter TAZ reach the count that is stored in the two memory sections S and S ^{* of} each output channel V ₁ to Vp, V ₁ , V ₂ , etc. appear at the output of the relevant output channel assigned comparator K _{1 '} K ₂ etc. a "1". This also applies if the count of TAZ is «0 and the relevant memory parts S and S ^{* are} empty. In all other cases there is a “0” at the outputs of the individual comparators K ₁ to Kp.

If we now activate the overall order, a general reset signal ensures that all output channels V ₁ to V _P , the age counters AZ ₁ to AZ _P assigned to them and the reference counter RZ are in the initial state, so that a “1” is given at the output of all comparators K ₁ to K _P and K ₁ ^* to Kp ^* .

Now. If a game key is pressed in the manual M, a “1” is entered into the register cell of the input shift register PSW assigned to it, while the register cells assigned to the game keys that are not actuated retain the state “0”. The clock pulses now starting to begin to push the "1" generated due to the game button pressed out of the input shift register, with each shift clock being counted in the tone address counter TAZ. Since the arrangement of the individual register cells in the input shift register PSW corresponds exactly to the arrangement of the game keys in the manual M, the number of shift clocks required until the appearance of the «1 at the data output of the input shift register PSW and the count in the tone address counter built up with them are TAZ is the address for the sound being played.

In order to transfer the count from the sound address counter TAZ into one of the output channels V ₁ to Vp, each of the inputs on one of the AND gates A ₁ to Ap must be assigned a «1. Since the information from the input shift register PSW is also shifted by the clock pulses TM, TS and TSS provided by the clock generator TG when the shift register cells are quasi-static register cells, it is automatically ensured that when a "1" arrives via the data input DE of the channel selector KW the input of the AND gates A ₁ to Ap also has a “1” pending on the input of these AND gates dedicated to the clock TM. Finally, since the AND gate UG _{1 has} only two inputs of all these AND gates UG ₁ to UG _P and one input of all of these AND gates with empty memories via the associated control output B ₁ or B ₂ or ..... or B _P is constantly supplied with a "1" and also the second input of all aND gate UG ₁ to UCP supplied by the inverter IV "1" is pending and the first output channel V ₁ associated aND gate UG ₁ alone has only two inputs, a «1 is only given at the output of this AND gate UG ₁ . This means that of the OR gates OD ₁ to ODp only the OR gate OD _{1 has} a “1” at the output. Thus, at the exit of the «1 out of the input shift register PSW can address ₁ and the enable its output channel, only the first output channel V ₁ corresponding AND gate A.

This means that the count present at the exit of the “1” from the input shift register PSW, that is to say the address of the sound being played, is adopted in the memory cells of the first output channel V ₁ . The result of this is that the "0" at the output of the comparator K ₁ disappears, that, in addition, a "0" appears at the feedback control output B _{1 of} the first output part V ₁ instead of the "1" previously present and that the second output channel V ₂ assigned AND gates UG ₂ all three inputs are assigned a «1». Because the "0" at the reverse control output B ₁ creates a "1" at the output of the logic cell L ₁₂ (given only by an inverter), so that a "1" is now pending at the output of UG ₂ , while the "1 »At the exit from UG _{1 has} now disappeared and at the outputs of the other AND gates UG ₃ to UGp the appearance of a« 1 is provisionally excluded.

Thus, when a next "1" is shifted out of the input shift register PSW, the count of TAZ which has been built up up to that point, and thus the tone address of the newly played tone, is adopted in the memory cells of the second output part V ₂ . The "1" thereby disappears on the reverse control output B ₂ of this channel V _2, thereby providing, via the logic cell L ₂₃ ensure that the three inputs of the next output channel V ₃ corresponding AND gate UG ₃ with a "1" until the arrival of next «1 from the output shift register PSW remain applied. The game is repeated successively on the respective subsequent output channel V ₄ to Vp until the addresses of the first p played tones are stored in one of the output channels and - as long as the memory state persists - ensures in the manner already described with reference to FIG. 2, that the tone frequency oscillation corresponding to the stored tone at the tone signal output AU ₁ or AU ₂ or ..... or AUp of the relevant output channel V ₁ or V ₂ or ..... or Vp to the respectively assigned amplitude former AF ₁ to AFp is delivered.

Now all channels V ₁ to Vp occupied by a respective been played tone, it must now be taken to ensure that the memory cells of at least one of the output channels V ₁ to Vp emptied through a low pulse. The generation of these branching deletion pulses representing TM pulses and their distribution to the individual output parts V ₁ to Vp of the switching system VM is now based on various aspects already mentioned. After the discussion of FIGS. 7 and 7, how the implementation takes place in the individual cases will be shown.

Each of the output channels V ₁ or ...... or Vp of the switching system VM shown in FIG. 2 controls an amplitude former AF ₁ or ...... AFp with its output. The structure of such an amplitude shaper is shown in FIG. 6.

After this, the output is AU ₁ or AU ₂ or .... or AUp of the relevant output part V ₁ to. V ₂ or ..... or Vp at the input of a shaping circuit FS, each of which is combined with a counter Z. With regard to the details of the shaping circuit FS and the counter Z can on DE-A-29 16 765 are pointed out. This patent application relates to a semiconductor circuit for the conversion of sequences of periodic AC signals with a signal input, a circuit part which effects the conversion and a signal output. Characteristic of this semiconductor circuit is the measure that the signal input is connected to the one current-carrying connection of several identical transistors and each of these transistors is combined with another such transistor to form a pair of transistors by the other current-carrying connection of the first transistor of each transistor pair with the Corresponding current-carrying connection of the associated further transistor is connected and is also connected to the signal output of the circuit via one of n different resistor combinations, that the resistor combinations respectively assigned to the individual transistor pairs form a resistor network and that the first current-carrying electrodes of the second transistors of all of these Transistor pairs are at a common and different from the reference potential (ground) operating potential and that finally to act on the control electrodes of the transistors has an n count stages Transmitter and digital counter controlled by a clock generator with counting pulses is provided and the n transistor pairs are connected in different ways from case to case with the signal outputs of the digital counter.

The dual counter Z assigned to the individual amplitude shaper AF ₁ to AFp is, as already explained in DE-A-29 16 765, designed as an up-down counter. In the example, it has 7 counting stages in the form of seven flip-flop cells connected in series, e.g. B. toggle flip-flop cells, which are each provided with two inputs, ie a direct and an inverted input. Each of the two inputs of the individual flip-flop cells forming the counter Z is connected to the gate of a respective MOS transistor of the enhancement type. The drains of the two MOS transistors assigned to a counting stage in this way are connected to each other and each connected via a resistor to a dividing point of a voltage divider provided by 8 resistors connected in series in the example. The source connections of the one of the two MOS transistors each assigned to a counter stage are connected to an average operating potential and the other transistor (assigned to the inverted input) with its source at the audio signal output AU ₁ or ..... or AUp of the respective one Amplitude shaper AF ₁ or .... or AFp assigned output channel V ₁ or .... or Vp of the switching system VM. Said voltage divider forms the signal output SG ₁ or ...... or SG _{P of} the relevant amplitude shaper at one end and is connected to the mean operating potential at the other end and thus to the source connections of the inputs of the individual which are acted upon in inverted fashion MOS transistors assigned to counting stages.

The signal outputs of the p provided amplitude formers AF ₁ to AF _P are each at an input of a mixing stage Mi, the output of which controls a loudspeaker LT, that is to say an electro-acoustic transducer, via an amplifier V. Details regarding the previously described parts of the amplitude shaping circuit shown in FIG. 6 need not be discussed further in connection with the present semiconductor circuit.

The count input of the up-down counter Z of the amplitude shaper is supplied by a system containing at least one oscillator for generating the counting clocks, the system itself being back-controlled by certain counts of the counter Z in question. In the example, two such oscillators OZ ₁ and OZ _{2 are} provided, which are designed in a manner known per se such that they deliver square-wave oscillations with an adjustable frequency. Each of these two oscillators OZ ₁ and OZ ₂ controls a frequency divider TL ₁ and TL ₂ , which in the example have three divider stages F ₁ to F ₃ and F ₄ to F ₆ in the form of flip-flop cells connected in series. In the example, master-slave flip-flops (toggle flip-flops) are used for the individual divider stages, so that the oscillations supplied by the respective oscillator OZ ₁ or OZ ₂ directly to one input of the first flip-flop cell and the other input is fed via an inverter (not specifically designated). These two oscillators OZ ₁ and OZ ₂ are common to all of the p amplitude shapers provided. They therefore control a total of p frequency dividers TL ₁ and p frequency dividers TL ₂ .

As a further component of the system for the generation of the counter clocks, at least two flip-flops and one which is controlled by certain counter readings of the binary counter Z via the flip-flops and the supply of the oscillations supplied by the divider stages as counter clocks for the counter Z, the logic from AND gates and OR gates combined is provided.

Here, in the in Fig. Exemplary case depicted 6 AND gates A ₁ to A with three signal inputs to mention first six _6, of which the three first the controlled from the oscillator OZ ₁ first divider TL ₁ and the last three which from the oscillator OZ ₂ controlled second divider TL _{2 are} assigned by an output, z. B. the non-inverted output, each divider stage F ₁ to F _{6 is} connected to an input of one of the AND gates a ₁ to a ₆ . Accordingly, e.g. B. the AND gates a ₁ to a _{3 to} the first divider TL, and the AND gates a _{2 to} the second divider TL ₂ . The outputs of all these AND gates a ₁ to a ₆ each go to an input of a common OR gate od. The output of this OR gate od is present a further AND gate ug, which has two inputs, one of which is controlled by said OR gate od and the other by one output of a flip-flop cell FF. The flip-flop LFF is acted upon at both inputs by an output of the logic circuit Lo. This logic circuit Lo is in turn controlled by the up-down counter Z and by a start signal St, which is also provided for starting the RS flip-flop formed by the two NOR gates n ₁ and n ₂ .

The up-down counter Z has seven counting stages in the example. It controls the logic circuit Lo with the counter reading «0» as well as with its highest count and with the highest count as well as with two additional counts one of the three AND gates a ₁ *, a ₂ * and a ₃ * (of course several such AND gates may also be provided), each having seven inputs and for the purpose of coding a specific count of the counter Z being acted upon by one of the two outputs Q and Q of each counter stage of Z. Here, the AND gate a1 * is assigned to a first count other than "0", the AND gate a ₂ ^{* to} a second - higher - count and the AND gate a ₃ * to an even higher third count of Z, which in particular corresponds to the corresponds to the highest count of this counter Z. On the output side, a differentiation stage DS _{2 is} assigned to the third AND gate a ₃ ^* , while the control by the other two AND gates a ₁ * and a ₂ * works without such a differentiation stage.

The AND gate a ₁ * is connected to an input of the aforementioned NOR gate n ₁ , which together with the NOR gate n _{2 forms} an RS flip-flop. For this purpose, its output is connected to an input of the NOR gate n ₂ and the output of the NOR gate n ₂ to an input of the NOR gate n ₁ . The first NOR gate n _{1 also} has a third input which is connected to a reset input of the circuit according to FIG. 6 which is controlled by reset signals. This reset input Re may also apply to the reset input of counter Z, so that when a reset pulse occurs it switches to the counter status "0" (if counter Z has not already been switched to "0" by the countdown phase). A gesteuertet by a start signal St is input via a differentiating stage DS, on the one hand to the logic Lo and on the other hand to a second input of the NOR gate with n ₁ cross-coupled NOR gate _N2. The output of the RS flip-flop formed by the NOR gates n ₁ and n ₂ is identical to the output of the NOR gate n ₁ . It is connected to an input of the AND gates a ₃ and a _e acted upon by the two last divider stages F ₃ and F _{e of} the two dividers TL ₁ and TL ₂ .

A second RS flip-flop is connected through the two NOR gates n ₃ to the output of the other NOR gate. A second input of the NOR gate n ₃ is at the output of the AND gate a1 *, a second input of the other NOR gate n _{4 is} at the output of the AND gate a ₂ * and a third input of the NOR gate n _{4 is} at the reset input Re the circuit. The output of the second RS flip-flop n ₃ , n ₄ is given by the output of the second of these NOR gates, that is to say by the output of the gate n ₄ . It is connected to an input of the AND gates a ₂ and a _5, respectively, which are acted upon by the two penultimate stages F ₂ and F _{4 of} the two dividers TL ₁ and TL ₂ .

A third RS flip-flop is provided by the two NOR gates n ₅ and n ₆ , of which in turn one input is fed back to the output of the other gate. Another input of the gate n ₅ is controlled by the output of the second AND gate a ₂ ^* and another input of the other NOR gate n ₆ by the output of the AND gate a ₃ ^* via a differentiating stage DS ₂ . A third input of the NOR gate n ₆ is at the reset input Re. Its output forms the output of the third RS flip-flop n ₅ , n ₆ . It is located at a respective input of the acted upon by the first divider stages F ₁ and F ₄ AND gates A ₁ and A. ₄

The output of the differentiating stage DS _{2, which} is controlled by the AND gate a ₃ ^*, is also connected to an input of a further flip-flop cell AFF, the second input of which is connected to the reset input Re. The output of the flip-flop AFF, which receives the level “1” when a signal occurs at the output of the differentiating stage DS _2, is connected to a last input of the AND gates a ₁ to a ₃ controlled by the first divider TL ₁ and via an inverter IR at a last input of the AND gates a ₄ to a ₆ controlled by the second divider TL ₂ .

The same output of the flip-flop cell AFF is also connected to the input of the counter Z which effects the conversion of the counter Z from the up to the down-counting operation. The other output of the flip-flop cell AFF can be used instead of the inverter IR to switch the third inputs of the To control AND gates a ₄ to a ₆ . The inverter IR is then not required.

The design of the logic circuit Lo shown in FIG. 7 has two AND gates controlled by the two extreme levels of the up-down counter Z, the AND gate u ₁ * being the highest, the AND gate u ₂ ^* the lowest count, that is to say the Count «0 is assigned. The AND gate u ₁ * can be identical to the AND gate a ₃ ^* , although in the case of the logic Lo the differentiation stage DZ _{2 is} not included. Since in the example the counter Z has seven counting stages, that is to say seven toggle flip-flop cells connected in series, the AND gates u ₁ * and u ₂ * each have seven inputs which, in the case of the AND gate u1 *, have those which indicate the count Outputs Q and in the case of the AND gate u ₂ ^* are each connected to the outputs Ö of the counter Z which carry the inverted signals.

The output of the "0" display The AND gate u ₂ * is connected via a differentiating stage DS ₃ to the one input of an OR gate org ₂ , the other input of which is controlled by a further AND gate ud ₃ and the output of which is applied to the flip-flop LFF that this blocks the AND gate ug controlling the supply of counting pulses to counter Z. The first-mentioned AND gate ud ₂ is acted upon on the one hand by the AND gate u ₁ * dedicated to the highest count of the counter Z (which is preferably identical to the AND gate a ₃ ^* ) and on the other hand by a control input P / S supplied signal. In the presence of such a signal (or its absence) it is achieved that the sound amplitude maintains its constant amplitude as long as the signal continues even when the play key is released.

The other input of the flip-flop cell LFF is controlled by a further OR gate org ₁ , which, in contrast to the OR gate org _1, ensures the supply of counting pulses to the counter Z via the AND gate ug. The OR gate org ₁ is also controlled by two AND gates ud ₁ and ud ₂ . One input of the AND gate ud _{2 is located} at the control input P / S already mentioned, while the other input is acted upon by an input TLO. A signal is given to the input TLO when the game button responsible for the current application of the considered amplitude shaper AF ₁ to AFp is released in the manual M. The generation of this signal, which controls the input TLO, will be discussed after the pending further consideration of the channel selector KW.

The other AND gate ud ₁ is connected with one input to the AND gate u ₂ * assigned to the count “0” of the counter Z and with the other input to the input St carrying the start signal, through which the NOR gate n ₂ is controlled. Since when the channel V ₁ or V ₂ or .... or Vp and the amplitude shaper AF ₁ or AF ₂ or .... or AF _P controlled by it, the up-down counter Z changes to the count «0 is, the OR gate org _{1 is} activated by the start signal supplied via the start input St and thus the flip-flop LFF is brought to an operating state in which the downstream AND gate ug for those supplied by the output of the OR gate od Counting cycles is permeable. The state is evidently ended when, due to the countdown in counter Z, the count reaches “0” and the AND gate u ₂ ^* thus sends a signal to the OR gate org ₂ by means of the differentiating stage DS ₃ connected downstream, by means of which the Flip-flop LFF flips to the other position and the AND gate blocks below.

In the same sense, when the AND gate u ₁ * coupled to the highest number of counters Z is applied and the signal input P / S, the AND gate ud ₃ acts, since this then also has the AND gate OR _2. Gate ug throttles. In the same way as the AND gate ud _1, the AND gate ud ₂ acts on the OR gate org ₁ and thus on the flip-flop LFF as soon as it is at its one input at the same time by releasing the game key in the manual when the relevant key is released M arising and supplied via the input TLO and at the other input by a signal P / S (z. B. generated by a pedal).

The differentiating stages DS ₁ , DS ₂ and DS ₃ can advantageously be designed in accordance with DE-A 28 45 379, since these trigger the immediate creation of a short defined pulse R due to a controlling pulse RZ. The task of these differentiation stages DS ₁ to DS ₃ is to be seen in the present case in that an extremely short pulse of defined length is triggered when a control pulse of any length occurs.

The start signals St are advantageously the takeover signals UE ₁ to UEp which are used to start the output part V ₁ to V _P assigned to the relevant amplitude former AF ₁ to AF _p and which are generated by the associated AND gate A ₁ to Ap of the channel selector KW used, so that expediently the output of the relevant output part V ₁ or .... or V _P AND gate A ₁ or .... or Ap to control the logic Lo in the downstream amplitude shaper AF ₁ or .... or AFp is used for the delivery of the start signal St. As already stated, they are brought to the NOR gate n ₁ as well as to the AND gate ud ₁ in the logic circuit Lo via the differentiating stage DS ₁ .

Due to the start signal St, a “1” appears at the output of the NOR gate n ₁ due to the specified conditions, which reaches one of the three inputs of the AND gate a ₃ controlled by the third divider stage F _{3 of} the plate TL ₁ . Furthermore, the flip-flop AFF is in a state in which the AND gate a. Is due to the initial state of the counter Z (be it because of a previous counting down to the count “0”, or because of a reset signal given via the reset input Re) ₁ to a ₃ can be loaded with a "1" by this flip-flop AFF. Finally, the two oscillators OZ ₁ and OZ _{2 are in} continuous operation (they can be switched on, for example, by the start signal St). Thus pass through the AND gate a ₃ , the OR gate od and the AND gate ug count pulses, which appear because they come from the last stage F _{3 of} the plate TL ₁ , with a relatively low frequency. These counts gradually increase the counter Z up to the count assigned to the AND gate a ₁ ^* . In the meantime, due to the control of the shaping circuit FS by the counter Z, the output part V, to Vp passed on from the shaping circuit to the mixing stage MI and from the respectively assigned output part delivered tone frequency signals increased successively, the amplitude being increased only relatively slowly due to the relatively slow enumeration of the counter Z.

If the AND gate a ₁ ^* now speaks when the counter Z, the counter Z assigned to it, has been reached, the «1» at the output of the NOR gate n ₁ disappears. In contrast, a «1» now appears at the output of NOR gate n ₄ . This has the consequence that the supply of the counting pulses supplied by the divider stage F ₃ is stopped and, instead, supplying from the divider stage F ₂ derived counts through the AND gate A ₂ is made possible because at the operating condition of both flip-flops LFF and AFF did not change anything and the St and Re entrances were no longer activated. Due to the counting pulses now appearing at a higher frequency than previously, the amplitudes of the sound signals supplied by the shaping circuit FS become larger faster than before, until the AND gate a ₂ ^* controlled by the higher count of the counter Z responds.

When the AND gate a ₂ ^* responds, the «1» at the output of the NOR gate n ₄ disappears and appears at the output of the NOR gate n ₆ . The supply of counting clocks from divider stage T _{2 is} thus ended and the AND gate a _{1 is} made continuous for the counting clocks originating from first divider stage F ₁ . As a result, the increase in the amplitude of the tone-frequency signals supplied at the output of the shaping circuit FS progresses even more rapidly than hitherto. When the count assigned to the AND gate a ₃ ^{* is reached} , the «1» at the output of the NOR gate n ₆ disappears. The flip-flop AFF is also flipped. This changes the counting direction in the counter Z. In addition, the AND gates acted upon by the oscillator OZ _{1 have} a ₁ to a ₃ in their effect for the delivery of the counter clocks by the. replaced by the oscillator OZ ₂ applied AND gate a ₄ to a ₆ .

First, however, only the state “0” is present at the outputs of the NOR gates n _{1 '} n ₄ and n ₆ which also control these AND gates a ₄ to a ₆ , so that for the time being no counting cycles reach the counter Z and the amplitude the audio frequency signals reaching the mixing stage Mi via the shaping circuit FS maintain their highest value. In order to end this state, the RS flip-flops formed by the NOR gates n ₁ to n _{6 must come} into action again, the flip-flop n _{1 '} n ₂ now having a higher counter reading than the flip -Flop n ₃ , n ₄ and the flip-flop n _s , n ₆ must end its action at the count «0. This means that the control of the AND gates a ₁ * _' a ₂ * and a ₃ * must be modified accordingly by the counter Z, or these AND gates must be replaced by AND gates which are controlled differently. The representation of the switching means required for this in words and pictures basically requires nothing other than the use of control means implemented by AND and OR combinations, which, based on a changeover or second start signal, the corresponding changeover by the NOR gates n ₁ to n ₆ formed three RS flip-flops and / or the AND gate acting on them. In the connection of these three RS flip-flops shown in FIG. 6, the NOR gate n ₁ would then have to be switched again to initiate the decay phase in such a way that a “1” appears at its output which, when the AND and Gate a ₁ ^* corresponding count of Z disappears again, while at the same time the «1» appears at the output of n ₄ . When the next lower count of Z assigned to the AND gate a ₂ ^{* is reached} , the «1 at the output of the NOR gate n ₄ disappears. Instead, the "1" appears at the output of the NOR gate n ₆ and disappears again as soon as the counter status "0" now assigned to the AND gate a ₃ * has been reached in the counter Z.

It is clear that even when this "reverberation effect" or also the sous-effect is achieved, the AND gate must be permeable for the counting cycles supplied by the OR gate od and therefore no "1" may be applied to the OR gate org ₂ . The conditions required for this can be read directly from Fig. 7. It should also be mentioned that the signals appearing at the output not connected to the AND gate below can be used as a sign that the counter has the count “O” and is therefore ready for recording.

At the end of the description of the channel selector KW according to FIG. 3, reference should be made to FIG. 8, in which the connection of the reference counter RZ already shown in FIG. 3 and the age counter AZ ₁ to AZp (in the example, p is again 10) is shown .

The control AST of the age counters AZ ₁ to AZp, which is only indicated in FIG. 3, that is to say in the example case AZ ₁ to AZ _10, is shown in FIG. 8.

Each age counter AZ ₁ to AZp is assigned to one of the intended output channels V ₁ to Vp of the switching system VM. In the exemplary embodiment shown in FIG. 8, its counting input is acted upon by the output of one AND gate UL ₁ or UL ₂ or ... or ULp. Furthermore, each of the age counters AZ ₁ to AZp can be reset to the count “0” by an erase signal L ₁ to Lp supplied by the respectively assigned amplitude shaper AF ₁ to AFp upon its return to the initial state and by a general reset signal (not shown).

All age counters have the same number of counting stages, which also applies to the reference counter RZ assigned to the age counters AZ ₁ to AZp. A comparator K ₁ * to Kp ^{* is} provided between the reference counter RZ and each of the intended age counters AZ ₁ to AZp, which has already been mentioned and which, if the counter reading of the reference counter RZ is the same as the individual age counter AZ ₁ resp. AZ ₂ , etc., that is to say it outputs a «1.

The AND gates UL ₁ to ULp allocated to the individual age counters AZ ₁ to AZp deliver the counting clock for the respective age counter. In the example, these AND gates UL ₁ to ULp each have three inputs. One of these is acted upon by the OR gate OD ^* shown in FIG. ₁ and controlled by the comparators K ₁ to K _{P of} the individual output channels V ₁ to V _P , which always supplies a “ ₁ ” when at least one of the output channels V ₁ to Vp is busy.

(If you want to have the age counters or their clock supply only activated when all channels V ₁ to Vp are occupied, you have to replace the OR gate OD ^* with a corresponding AND gate.)

A circuit arrangement TLO ₁ to TLOp is also assigned to each of the output channels V ₁ to V _P and thus to each of the age counters AZ ₁ to AZ _P. B. can be configured according to FIG. 9 and which responds when the game button causing the application of the individual channel V ₁ to Vp and thus the respectively assigned age counter AZ ₁ to AZ _{P is} released again. It supplies a signal which is provided for controlling the second input of the AND gate UL ₁ or UL ₂ etc. of the individual age counters AZ _{1 '} AZ ₂ etc. so that the age counter AZ ₁ or AZ ₂ etc. only then receives counting pulses when the key is released or the effect of the named circuit parts is blocked by a (common signal) P / S. The third inputs of the individual AND gates UL ₁ to ULp are acted upon together by counter clocks. These counting cycles can e.g. B. be supplied by the clock TG controlling the input shift register PSW.

As a result of the connection of the AND gates UL ₁ to ULp just described, it is understandable that that counter has the highest count at which the continuous signal supplied by the switching element TLO has the longest effect.

The outputs of the AND gates UL ₁ to UL _P assigned to the individual age counters AZ ₁ to AZp are each connected to an input of a common OR gate oe, the output of which supplies the counting clocks for the reference counter RZ. Thus, each of the counting cycles supplied to one of the age counters AZ ₁ to AZp also serves as a counting cycle for the reference counter RZ.

As already mentioned above, a comparator K ₁ * to Kp ^{* is} provided between the reference counter RZ and each of the age counters AZ ₁ to AZp. The output of these comparators K ₁ * to Kp * serves on the one hand to control one AND gate A, * to Ap *. On the other hand, it is used by means of an inverter IR ₁ or IR ₂ or .... IR _P to control the reset input of the age counter AZ ₁ or AZ ₂ etc., which for this purpose from the output of the associated inverter IR ₁ to IR _P via a Differentiation stage ds ₁ or ds ₂ or ... or dsp is subjected to a short reset pulse if the «1 on the associated comparator K ₁ * or K ₂ * etc. disappears. The output of the individual inverters IR ₁ to IR _P acted upon by the comparators K ₁ * to Kp * is also connected to an input of an AND gate assigned to all the comparators K ₁ * to Kp * at ₁ .

The reference counter RZ is designed as an up-down counter, which is switched on the basis of a signal supplied by the AND gate at ₁ in the opposite counting direction and which in the absence of such a signal immediately tilts back into the up-counting direction. The output of the AND gate at ₁ is also at an input of a further AND gate at ₂ , the output of which is at a further input of the OR gate OR oe controlled by the AND gates UL ₁ to UL _P and the other input of which is Clock pulses, e.g. B. is controlled by the clocks TM.

Thus, if a reversal of the counting direction of the reference counter RZ occurs as a result of a “1” at the output of the AND gate at ₁ , then this receives via the AND gate at ₂ counting cycles until another of the comparators, namely the comparator that corresponds to the age counter is allocated with the highest count, receives a “1” at its input. so that the equality of the count of the reference counter with the count of one of the age counters AZ ₁ to AZ _{P is} restored.

The response of the individual comparators K ₁ * to Kp *, that is to say the appearance of a “1” at their output, means, as repeatedly emphasized, that there is equality between the count of the reference counter RZ and the count of an age counter. An exception is the initial state, since then not only one comparator, but all supply a "1", so that for this reason alone the reference counter RZ is initially kept at the count "0". After the first output channel V _{1 has been applied} , the OR gate OD ^* responds. The first counting cycle for an age counter AZ ₁ to AZ _P is only due when one of the circuit parts TLO ₁ to TLOp responds. Because of the dependency of the counting clocks on the third inputs of the AND gates UL ₁ to ULp, which originate from a common clock generator and are therefore synchronous to one another, UL ₁ or .. UL2 or ... or ULp is the counting clock which is acted upon by the signal TLO, that is to say by the respectively associated indicator TLO ₁ to TLO _P. These counting clocks then arrive both at the counting input of the age counter belonging to the AND gate UL ₁ to ULp, which is now permeable to the counting clocks, and via the OR gate oe at the counting input of the reference counter RZ, so that both counters builds up the same count.

Is now loaded a second channel and the loading of this channel, for. B. the channel V ₂ causing game button released, so receives the age counter assigned to this channel, i.e. in the example the age counter AZ _{2 '} now also the synchronous counting impulses, so that this age counter AZ ₂ and in all other age counters belonging to a busy output channel and acted upon by one of the signals TLO each have an individual count builds up, the lower the later the age counter in question was acted on by the TLO signal assigned to it.

An erase pulse generated by the first responding output channel V ₁ or by its amplitude shaper and applied to the reset input of the age counter AZ ₁ ensures that the count of the age counter with the highest count is deleted. Thus, the "1" at the output of the associated comparator K, ^* etc. disappears, so that the reference counter RZ corresponds to the count of the age counter which has the next highest count, e.g. B. the age counter AZ _{2 is} reset. Then he speaks this age counter, e.g. B. the age counter AZ ₂ associated comparator, that is, the comparator K ₂ , with a “1” at its output, so that the countdown of the reference counter RZ is ended abruptly. The following counts are then in a positive sense both on the age counter which now has the highest count, e.g. B. AZ ₂ , and the reference counter RZ, until AZ ₂ is reset to the count “O” by an erase signal L ₂ supplied by the associated channel V ₂ or the amplitude shaper AF ₂ . If, for example, the age counter AZ _{5 is} the age counter with the next highest count, the process described is repeated with this, by resetting the reference counter to the count of this age counter AZ ₅ , then by positive loading with the common counting clock synchronously with the new age counter AZ ₅ is counted up; until the count of this counter is also cleared by a clear signal L ₅ originating from the amplitude shaper AF _S and the reference counter RZ is set to a new count, namely the next highest count.

Since the deletion of the age counter is synchronized with the deletion of the sound address stored in the memory parts S and S ^{* of} the assigned output channel V ₁ , Vp, the channel that has become free can be re-acted upon, as has already been described above. If this tone address has been deleted due to the age-related decay of the played tone without a newly played button and a "takeover" signal being the moment triggering the delete signal, this means that NO (FIG. 3 ) no "1" is pending and therefore the newly assigned output channel can be reassigned in the manner already described, by means of the assigned AND gate from the row of AND gates UG ₁ to UGp. If, on the other hand, all channels V ₁ to Vp are occupied and at least one game button has already been released, control of AND gates A ₁ to Ap or the OR gates OD ₁ to ODp assigned to them occurs through AND gates A1 * to Ap ^{* in} force.

The age counter-controlled comparator K ₁ * or K ₂ ^* etc., which has the highest count, has a “1” at its output, while all other of these comparators have an “O” at the output. If the AND gates A ₁ * to Ap ^* which are provided with two inputs in FIG. 3 are each provided with a third input, this third input is controlled by a common overwrite signal US and that at the output of the individual AND gate A ₁ * to Ap ^* supplied signal is not only used to control the associated OR gate from the series of OR gates OD ₁ to ODp, but also uses this signal as a second erasure signal for the content of the memory parts S and S ^* of the associated output channel. This automatically ensures that when an overwrite signal ÜS is applied to the entirety of AND gates A ₁ * to Ap ^* with fully occupied output channels V ₁ to Vp, the channel with the most waning tone signal in the assigned amplitude shaper is immediately cleared and by the newly played Tone signal is busy.

A circuit for generating the TLO signal is shown in FIG. 9. Here, the data input DE of the channel selector KW and the comparator K _{1 are} each connected to one input of an AND gate 1 and one input of a NOR gate 2. The output of the AND gate 1 controls the. Reset input R of an RS flip-flop 3, the output of the NOR gate the set input S of this flip-flop 3. The Q output is at an input of a further AND gate TLO ₁ ; the output of which provides the signal TLO. The second input of the AND gate TLO ₁ is controlled via an inverter through the input P / S.

Since there is exactly one coincidence of a "1 at the output of the comparator K _{1 in question} and a" 1 at the data input DE during each counting period of the sound address counter TAZ, provided that the game button on channel V _{1 is} still pressed, the output Q of the RS -Flip-flops 3 are given a permanent “1 only when the“ 1 ”at the data input DE no longer appears at the time when the comparator K ₁ etc. responds, that is, in other words, the game button in question has been released.

10 shows a possibility for supplying the individual output channel (V ₁ ,... Vp) with the sound address stored in the age-related deletion of the sound address stored in the relevant output channel on the basis of a respective amplitude former (AF ₁ ,... AFp) Deletion pulse or a deletion pulse to be supplied when the stored information is prematurely replaced by new information.

einsam mit dem für die Dauer des Betriebszustandes der Rückwärtszählung durch das Flip-Flop AFF (Fig.6) gesteuerten Steuereingang des Vorwärts-Rückwärtszählers Z beaufschlagt ist. Demzufolge spricht das UND-Gatter u₃* nur dann an, wenn bei Rückwärtszählung der Zählstand « O » in dem Zähler Z erreicht wird.That added the up-down counter (Z) in the single amplitude shaper (AF ₁ , ... AFp) The AND gate u ₂ ^{*, which} responds at the count “0”, has its output connected to the one input of a further AND gate u ₃ ^* , the other input of which is

lonely with the control input of the up-down counter Z controlled by the flip-flop AFF (FIG. 6) for the duration of the operating state of the down-count. As a result, the AND gate u ₃ * only responds if the count “O” in the counter Z is reached when counting down.

The "1" that arises at the output of the AND gate u ₃ ^* can, for. B. via an OR gate OT to the common reset input of the two memory parts S and S ^* (z. B. to the gate of the transfer transistors t ₄ in an embodiment according to FIG. 5). On the other hand, the OR gate OT is also from the output of the respective associated output channel (V ₁ , ... Vp) and from the assigned age counter (AZ ₁ , ... AZp) or from the comparator (K ₁ , ... Kp ^* ) controlled AND gate A, ^* , ... Ap ^* forth, which, as already explained, responds to fully occupied output channels V ₁ , ... Vp and due to an overwrite signal US.

It should also be noted that even in the case of the present digital circuit, a system designed in a known manner for generating a general reset pulse can be provided. 10 that the delete signal output at the output of the OR gate OT is in any case - e.g. B. by tilting the flip-flop AFF into the other operating state and by resetting the RS flip-flops n ₁ , -n ₆ to the initial state (the signal L then represents the reset signal Re indicated in FIG. 6) - is used to also spontaneously reset the amplitude shaper F _{1 '} ... AFp assigned to the respective output channel V ₁ , ... Vp to the initial state.

It will be understood that modifications of the described embodiment of a digital semiconductor circuit according to the invention are now possible for the person skilled in the art reading the above information.

Claims (39)

1. A digital semiconductor circuit for an electronic organ, with a number of control inputs, which can be operated via the keyboard, the number of which corresponds to the number of keys of the organ keyboard, and with a number of sound signal inputs which are acted upon by an oscillator system with periodic electrical oscillations, wherein one control input is in each case permanently assigned to one key of the keyboard, and one sound signal input is in each case permanently assigned to one sound frequency, wherein moreover a sound signal output is provided for connection to an electro-acoustic transducer, and wherein finally the control signals, which act upon the control inputs, correspond to logic levels, characterised in that the individual control inputs (Ey) are each assigned to one cell of a clockpulse-controlled shift register (PSW) which is operated as a parallel-series converter, that moreover, both the signal output (DA) of the shift register (PSW) and the clock pulses provided for the operation thereof, serve to control an exchange system (VM) which comprises all the provided sound signal inputs (TSE) and the sound signal outputs (AU₁ ... AUp), the number p of which is lower than the number of control inputs (Ey), that each of the sound signal outputs (AU₁ ... AUp) is assigned an amplitude shaper (AF₁ ... AFp) and that finally the outputs (AG, ... AGp) of the amplitude shapers are connected to an electro-acoustic transducer (L).

2. A digital semiconductor circuit as claimed in claim 1, characterised in that the signal output (DA) of the shift register (PSW) is connected to the data input (DE) of a channel selector (KW), and the channel selector (KW) serves, with, in each case, one of its outputs (UE,, UE₂ ... UEp) to control one of p output sections (V₁, V₂ ... Vp) of the exchange system (VM), that moreover by way of further information input of the exchange system (VM), in addition to the data input (DE) of the channel selector (KW), the input of a sound address counter (TAZ) is provided, which is controlled by the shift clock pulses for the shift register (PSW) as counting clock pulses, and which acts upon each of the output sections (V₁ to Vp) of the exchange system (VM) in the same way.

3. A digital semiconductor circuit as claimed in claim 2, characterised in that each of the output sections (= output channels) (V₁ to Vp), which are identical to one another, is connected in an identical fashion to each of the sound signal inputs (TSE₁ ... TSE₁₂) which is acted upon by the oscillator (TOS).

4. A digital semiconductor circuit as claimed in claim 2 or 3, characterised in that the oscillator (TOS) is designed in such manner that it makes available the sound frequencies, assigned to the sounds of the highest octave, in the form of rectangular oscillations with the logic levels « 1 » and « 0 » at in each case one sound signal input (TSE₁ ... TSE₁₂) of the exchange system (VM), and that each of these twelve sound signal inputs is connected to each of the p provided output sections (V₁ to Vp) of the exchange system (VM).

5. A digital semiconductor circuit as claimed in the claims 2 to 4, characterised in that each of the output sections (V₁, ... Vp) of the exchange system (VM) is provided with a reset control output (B₁ ... Bp) by means of which a reaction of the relevant output section (V₁ ... Vp) of the exchange system (VM) on the channel selector (KW), and possibly an additional control action on the amplitude shaper (AF₁ ... AFp) assigned to the relevant output section, is possible.

6. A digital semiconductor circuit as claimed in the claims 2 to 5, characterised in that the sound address counter (TAZ), which is acted upon by the shift clock pulses (T) of the input shift register (PSW), comprises two sections, that moreover each of the provided p output sections (V₁ ... Vp) of the exchange system (VM), as information input section, contains a write-read store which is controlled both by the channel selector (KW) and by the sound address counter (TAZ), that this writeread store comprises two sections (S, S^*), that moreover the first section (S) of all these stores is acted upon by the first section of the sound address counter (TAZ) and the second section (S^*) is acted upon by the second section of the sound address counter (TAZ), and that finally the first section of the sound address counter and the associated store section (S) serve to control the exchange system (VM) on the basis of the sound name, whereas the second section of the sound address counter and the associated store section (S^*) serve to control the exchange system (VM) on the basis of that octave of the. keyboard (M) which includes the sound which has been played.

7. A digital semiconductor circuit as claimed in claim 6, characterised in that the first section of the sound address counter (TAZ) comprises four counter stages arranged in series, and the second section comprises at least three counter stages arranged in series, that here the counting input of the first counter stage of the first section of the sound address counter (TAZ) is acted upon by the shift clock pulses, which are intended to operate the input shift register (PSW), in the same way as the clock pulse input of the shift register (PSW), that moreover the counting input of the second section of the sound address counter (TAZ) is connected to those outputs of the counter stages of this sound address counter section which switch through the count of the first section of the sound address counter, that the second section of the sound address counter (TAZ) receives a counting pulse only when the count of the first counter section, which is initially at « 0 », has increased by the amount « 12 ».

8. A digital semiconductor circuit as claimed in claim 7, characterised in that the first section (S) of the write-read store, which is provided in the individual output sections (V₁, ... Vp) of the exchange system (VM) comprises for example four storage cells, whereas the second section (S^*) comprises for example three storage cells, that the information input of the storage cells of the first store section (S) serves to receive the count of the first section, whereas the information input of the storage cell of the second store section (S^*) serves to receive the count of the second section of the sound address counter (TAZ), that moreover the content of the first store section (S) serves to control the reception of the items of information, present at the sound signal inputs (TSE₁ ... TSE₁₂) of the exchange system (VM), by the individual output channel (V₁ ... Vp) of the exchange system (VM), and the content of the second store section (S^*) serves to control the forwarding of these items of information to the sound signal output (AU, ... AUp) of the relevant output channel (Vi ... Vp) of the exchange system (VM).

9. A digital semiconductor circuit as claimed in claim 8, characterised in that a first decoder (D), which is controlled by the storage cells of the first store section (S), and a second decoder (D^*), which is controlled by the storage cells of the second store section (S^*) are provided in each output section (V₁ ... Vp) of the exchange system (VM), that each of the outputs of the first decoder (D) is connected to the first input of each AND-gate (U₁, U₂ ... U₁₂), whose second input is controlled by one of the sound signal inputs (TSE), which are acted upon by the oscillator (TOS), of the exchange system (VM), and whose output is connected to one of the inputs of a first OR-gate (0), that moreover each of the outputs of the second decoder (D^*) is connected to the first input of an AND-gate (U*₁, U^* ₂ ... U^* ₆), whose second input is controlled in a different manner via the output of the first OR-gate (0), and whose signal output is in each case connected to one of the inputs. of a second OR-gate (0^*) which forms the sound signal output of the circuit section in question, and thus forms one of the p sound outputs (AU₁, AU₂ ... AUp) of the exchange system (VM).

10. A digital semiconductor circuit as claimed in claim 9, characterised in that the signal output of the first OR-gate (O) of each output section (V₁ ... Vp) of the exchange system (VM) is connected on the one hand to the first input of an AND-gate (U*₁) controlled by the second decoder (D*), and on the other hand. to the signal input of a frequency divider (TT), that here fhe number of divider stages of the frequency divider (TT) is at least equal to the number of signal outputs, reduced by one, of the second decoder, and that the signal outputs of at least the first divider stages are each connected to another of the AND-gates (U^* ₂ ... U^* _e) which are controlled via the second decoder (D^*).

11. A digital semiconductor circuit as claimed in the claims 8 to 10, characterised in that the two store sections (S, S^*) in each of the output channels (V₁ ... Vp) of the exchange system (VM) are controlled by the channel selector (KW) via a control input (UE₁, UE₂ ... UEp) assigned to the output channel in question.

12. A digital semiconductor circuit as claimed in the claims 8 to 11, characterised in that each of the storage cells of the two store sections (S, S^*) in the individual output channels (V₁ ... Vp) is monitored in respect of signal input from the sound address counter (TAZ) and in respect of signal output to the decoder (D, D*) by means of a comparator (K₁ ... Kp) which is in each case assigned to the output channel (V₁ ... Vp) in question, and that the individual comparators (K₁, K₂ ... Kp) are such that in the event of identity of the count of the sound address counter (TAZ) with the count which is stored in the two store sections (S, S^*) of the relevant output channel (V₁, V₂ ... Vp) and which represents the sound address of the key which acts upon the output channel in question, said comparators emit the signal « 1 », but otherwise, a « 0 » appears at the output of these comparators.

13. A digital semiconductor circuit as claimed in the claims 8 to 12, characterised in that the two store sections (S, S^*) in the output channels (V₁ ... Vp) comprise storage cells (S₁, S₂) which are not connected to one another and whose data inputs are each connected to an output - which switches through the count - of the sound address counter (TAZ), and whose data outputs are each connected to an input of the decoder (D, D^*) which is to be acted upon by the storage cell in question.

14. A digital semiconductor circuit as claimed in claim 13, characterised in that the individual storage cells (S₁, S₂) of the two store sections (S, S*) of the individual output channels (V₁ ... Vp) comprise clock-pulse-controlled, quasi-static shift register cells (Fig. 7).

15. A digital semiconductor circuit as claimed in claims 4 and 9, characterised in that the outputs of the first decoder (D) are each logic- linked to a sound signal input (TSE₁ ... TSE₁₂), which are each assigned to one sound of the highest octave and are acted upon by the sound generator (TOS) which supplies the correspond-. ing rectangular oscillations, by means of an AND-gate (U₁ ... U₁₂) having two inputs, that moreover the outputs of these AND-gates (U₁ .... U₁₂) are each connected to an input. of an OR-gate (0), and the output of the latter is connected to the clock pulse input of a frequency divider (TT) having a number of divider stages which corresponds to the number, reduced by one, of provided octaves, and that the sound-frequency oscillations which are supplied from the output of the OR-gates (O) directly and via the divider stages of the frequency divider (TT) are each connected to an input of an OR-gate (O^*), which forms the output (AU₁ ... AUp) of the relevant output signal (V₁ ... Vp) in a manner controlled by the second decoder (D^*).

16. A digital semiconductor circuit as claimed in claim 15, characterised in that the output of the OR-gate (0), which is controlled by the first decoder (D), and the signal output of each divider stage of the frequency divider (TT) are each logic- linked to an output of the second decoder (D^*) via an AND-gate (U*₁ ... U*_p), and the output of each of these AND-gates (U*₁ ... U*_p) is connected to an input of the OR-gate (O^*) which forms the sound signal output (AU₁ ... AUp) of the relevant output channel (V₁ ... Vp).

17. A digital semiconductor circuit as claimed in the claims 1 to 16, characterised in that in the amplitude shapers which are assigned to the individual sound signal outputs (AU₁ ... AUp) of the exchange system (VM) there is arranged a shaper circuit (FS) which is acted upon by' the relevant sound signal output and which is controlled by a forwards-backwards-counter (Z) and which is connected by its output to a mixer stage (Mi) which is common to the individual sound signal outputs and which is followed by an electro-acoustic transducer (L.) (Fig. 6)

18. A digital semiconductor circuit as claimed in claim 17, characterised in that for the generation of the counting pulses, which are required for the forwards-backwards counters (Z) which control the shaper circuit (FS) in the individual amplitude shapers (AF, ... AFp), there is provided an oscillator (OZ₁, OZ0 which is common to all the amplitude shapers of the circuit and which supplies the counting clock pulses required for the forwards-backwards counter (Z) in question via a logic circuit which is controlled individually in the individual amplitude shapers (AF, ... AFp) and via at least one frequency divider (TL₁, TL₂).

19. A digital semiconductor circuit as claimed in claim 18, characterised in that the counting outputs of the forwards-backwards counter (Z) in the individual amplitude shapers serve for example to control three RS-flip-flops (n₁, n₂ ; n₃, n₄ ; n_s, n₆) each of which respond at a specific count and at one output, control the conductivity of, in each case, one AND-gate (a, ... a₆) for a sequence of counting pulses supplied by the oscillator (OZ₁, OZ₂ via the divider stages of at least one of the frequency dividers (TL₁, TL₂), for forwarding to the counter (Z), and that one input of a logic circuit (Lo), which is controlled at another input by (an over) various signals (St, P/S, u*₁, u*₂ which serve to operate the entire circuit, is acted upon by the counter (Z) with a signal which displays the count « O » and the maximum count.

20. A digital semiconductor circuit as claimed in claim 19, characterised in that when the maximum count is reached in the forwards-backwards counters (Z) of the individual amplitude shapers (AF, to AFp), a further flip-flop (AFF), which is controlled via the RS-flip-flops (n, ... n₆) is switched over from its first operating state, which is assigned to the upwards counting direction of the forwards-backwards counter (Z), into the second operating state, which is assigned to the the backwards counting direction of this counter (Z) ; and the signal which is formed at its output as a result of this switch-over is used to switch-over the counter into the backwards counting direction.

21. A digital semiconductor circuit as claimed in the claims 18 to 20, characterised in that the reaching of the count « 0 during the backwards counting operation of the forwards-backwards counter (Z) in the individual amplitude shapers is linked to the emission of an erasing pulse (L₁ ... Lp) which sets into the starting-state the operating state of the output channel (V₁ ... Vp), in each case assigned to the amplitude shaper (AF₁ ... AFp) in question, of the exchange system (VM) (Fig. 8).

22. A digital semiconductor circuit as claimed in claim 21, characterised in that the outputs (Q) of the forwards-backwards counter (Z), which display the inverted count, in the individual amplitude shapers (AF₁ ... AFp) act upon an AND-gate (u^* ₂) which responds when all these outputs have a count of « O », and only then, that moreover the output of this AND-gate (u*₂ serves to control the first input of a second AND-gate (u^* ₃) whose other input, together with the control input which controls the backwards counting direction, is controlled in particular by the flip-flop (AFF) which is itself controlled by the RS-flip-flop (n₁ ... n₆), controlled by the counter (Z), and whose output serves to emit an erasing signal (L) for the sound address stored in the particular assigned output channel (V₁, Vp) (Fig. 10).

23. A digital semiconductor circuit as claimed in the claims 5 to 22, characterised in that for the formation of a channel selector (KW), the data input (DE), which is connected to the signal output (DA) of the input shift register (PSW) is connected to a number of AND-gates (A₁ ... Ap), corresponding to the number (p) of the output channels (V₁ ... Vp), each having two inputs, the second input of which is controlled by a reset output (B₁ ... Bp) of the assigned output channel (V₁ ... V_p), which output conducts the signal « 0 » when the output channel (V₁ ... Vp) is engaged, and conducts the signal « 1 » when the output channel is unengaged, and whose output causes a count, which corresponds to the sound addresses of the key which produces the next « 1 » at the data input (DE) of the channel selector (KW) to be transferred from the sound address counter (TAZ) into the store (S, S^*) of the relevant output channel (V₁, Vp) (Fig. 3)..

24. A digital semiconductor circuit as claimed in claim 23, characterised in that the outputs of the two store sections which indicate the particular stored information content in the store sections (S, S^*) of the individual output channel (V₁ ... Vp) are connected to a common NOR-gate (NR) whose output forms the reset output (B₁ ... Bp) of the output channel (V₁ ... Vp) in question (Fig. 2).

25. A digital semiconductor circuit as claimed in the claims 23 and 24 characterised in that the second input, which is not connected to the data input (DE), of the AND-gates (A₁ ... Ap), which bring about the information transfer from the sound address counter (TAZ) into the assigned output channel (V₁ ... Vp) are each controlled by a further AND-gate (UG₁ ... UGp) which is likewise assigned to the relevant output channel (V₁ ... Vp), that each of these further AND-gates (UG₁ ... UGp) has a first signal input, which is controlled by the reset output (B₁ ... Bp) of the assigned output channel, and a second signal input, which is controlled by all the provided output channels (V₁ ... Vp) via a common AND-gate (NO, IV) and that, with the exception of the AND-gate (UG₁) assigned to the first output channel (V₁), the remaining AND-gates (UG₂ ... UGp) have a third input via which, in each case via a logic unit (L₁₂ ... L _(p-1)p), a sequence is controlled in the operation of the individual output channels (V₁ ... Vp) (Fig. 3).

26. A digital semiconductor circuit as claimed in claim 23, characterised in that the reset output (B₁) of the first output channel (V₁) is connected via an inverter (L₁₂) to the third (free) input of the AND-gate (UG₂) which is assigned to the second output channel and which is directly acted upon by the reset output (B₂) of the second output channel (V₂), that moreover the .... between the first and the last (UG₁, UGp) of the AND-gates (UG₂ ... UGp), which are directly controlled by the reset output (B₂ ... Bp) of the assigned output channel (V₂ ... Vp) are each connected via their free, third input to the input of an inverter (L_23a ... L_(p-1)pa)_' that moreover the output of this inverter and the reset input of the associated AND-gate (UG₂ ... UGp) are each connected to an input of a NOR-gate (L_23b ... L_(p-1)pb) whose output is connected to the free, third input of the AND-gate (UG₃ ... UGp) which is assigned to the next channel (V₃ ... Vp) and is directly acted upon by the latter via its reset output (B₃ ... Bp) (Fig. 4).

27. A digital semiconductor circuit as claimed in the claims 23 and 26, characterised in that between the AND-gates (A₁ ... Ap) which cause the assigned output channel (V₁ ... Vp) to be acted upon by the common sound address counter (TAZ), and second AND-gates (UG₁ ... UGp) assigned to the same channel (V₁ ... Vp) there is in each case arranged an OR-gate (OD₁ ... ODp) whose output is connected to the input, which is not acted upon by the data input (DE), of the ADN- gate (A₁ ... Ap) which causes information to be input into the assigned output channel (V₁ .... Vp) and simultaneously, by emitting a start signal (St) to the assigned amplitude shaper (AF₁ ... AFp) causes the latter to be set in operation, and whose first input is acted upon by the output of the AND-gate (UG₁ ... UGp) which is directly controlled by the reset output (B₁ ... Bp) of the assigned output channel (V₁ ... V_p) (Fig. 3).

28 A digital semiconductor circuit as claimed in the claims 23 to 27, characterised in that the outputs of the comparators (K₁ ... Kp), which are assigned to the output channels (V₁ ... Vp), are provided either for the control of a common OR-gate (OD^*) or of a common AND-gate.

29. A digital semiconductor circuit as claimed in the claims 23 to 28, characterised in that each of the provided output channels (V₁ ... Vp) is assigned an age counter (AZ₁ ... AZp), that moreover a common reference counter (RZ) is provided which is identical to the age counters (AZ₁ ... AZp) in respect of the number of counter stages, and which is designed as a forwards-backwards counter, that moreover for each of the age counters (AZ₁ ... AZp) arid the common reference counter (RZ) there is provided a comparator (K*₁ ... K*_p) which responds to the identity of the counts of reference counter (RZ) and assigned age counter (AZ) and via whose output it is possible to re-seize the assigned output channel (V₁ ... Vp), triggered by a signal (US), via the OR-gate (OD₁, OD₂ ... ODp) which is arranged between the two AND-gates (A₁, UG₁ : A₂, UG₂; ... A_p, UG_p) which are assigned to the output channel (V₁ ... Vp) in question (Fig. 3, Fig. 8).

30. A digital semiconductor circuit as claimed in claim 29, characterised in that the output of the comparators (K*₁ ... K*_p), which are assigned to the individual age counters (AZ₁ ... AZ_p) is connected, in each case via an AND-gate (A*₁ ... A*_p), to a second input of the OR-gate (OD₁ ... ODp) which controls the AND-gate (A, ... Ap) which itself effects the information input into the assigned output channel (V₁ ... V_p).

31. A digital semiconductor circuit as claimed in claim 30, characterised in that the AND-gate (A*₁ ... A*_p), which is in each case connected to the output end of the individual comparator (K*₁ ... K^*p), is co-controlled at a second input by the reset outputs (B₁ ... B_p) of all the output channels (V₁ ... Vp) via a common NOR-gate (NO).

32. A digital semiconductor circuit as claimed in the claims 30 and 31, characterised in that the AND-gate (A*₁ ... A*_p), which is connected following the individual comparator (K*₁ ... K*_p) and forms the connection to the AND-gate (A₁ ... Ap) which acts upon the assigned output channel (V_i ... Vp), is controlled, in common with the other of these AND-gates (A*₁ ... A*p), at a third input by the signal (US), which serves for overwriting purposes, and that the signal which then appears at the output of this AND-gate (A*₁ ... A*_p) is used to erase the SOUND-address stored in the particular assigned output channel (Fig. 8).

33. A digital semiconductor circuit as claimed in claim 32, characterised in that the output of the AND-gate (A*₁ ... A^* _p), which is connected to the output end of the comparator (K*₁ ... K*_p), which is assigned to the individual age counters (AZ₁ .... AZp), is connected via an OR-gate (OT) to the erase input of the store sections (S, S^*) arranged in the associated output channel (V₁ ... Vp) and that another input of the aforementioned OR-gate (OT) is acted upon by the erase signal (L) which is supplied by the amplitude shaper (AF₁ ... AFp) in each case assigned to the relevant output channel (V₁ ... V_p) (Fig. 10).

34. A digital semiconductor circuit as claimed in claim 33, characterised in that the erase signal (L), which serves to erase the sound address sotred in one of the output channels (V₁ ... Vp) and which is supplied by the associated amplitude shaper (AF₁ ... AFp), or an erase signal produced on the basis of an overwrite signals (ÜS), is simultaneoulsy used to erase a count which may be contained in the associated age counter (AZ_{1 ..}. AZ_p).

35. A digital semiconductor circuit as claimed in the claims 29 to 33, characterised in that the counting input of each age counter (AZ₁ ... AZp) is supplied with counting clock pulses via the output of an AND-gate (UL, ... ULp), that the counting input of the reference counter (RZ) is supplied with counting clock pulses via the output of an OR-gate (oe), that here the output of the AND-gates (UL₁ ... ULp), which are assigned to the individual age counters (AZ₁ ... AZp), is in each case connected to an input of the OR-gate (oe) which supplies the reference counter (RZ) with counting clock pulses, that moreover the AND-gates (UL, ... ULp), which supply the counting clock pulses for the individual age counters (AZ₁ ... AZp) and thus for the reference counter (RZ), each have three inputs, of which one is acted upon by an OR-gate (OD^*) which is commonly controlled by the reset outputs (B₁ ... Bp) of the output channels (V₁ ... Vp) (or a correspondingly connected AND-gate), the second is acted upon by clock pulses (TG) which appear synchronously at all these AND-gates (UL₁ ... ULp). and the last is acted upon by a circuit section (TLO₁ ... TLO_p) which is assigned to the relevant age counter (AZ₁ ... AZp) and which responds on the release of that key of the keyboard (M) which acts upon the output channel (V₁ ... Vp) which is assigned to the age counter in question (Fig. 3, Fig. 8).

36. A digital semiconductor circuit as claimed in the claims 29 to 35, characterised in that the comparators (K^* ₁ ... K^*p), which are each assigned to the individual age counters (AZ₁ ... AZp), are each provided to produce an erase signal for the count of the age counter and a further signal which serves to reset the count of the reference counter (RZ) to the count of the age counter which is provided with the next higher count, and which signal appears at the output end in the comparator having the age counter which has the highest count.

37. A digital semiconductor circuit as claimed in claim 36, characterised in that the output of the individual comparators (K*₁ ... K*_p) is in each case connected via an inverter (lR₁ ... IRp) and a differentiator stage (ds₁ ... dsp) to the erase input of the assigned age counter (AZ₁ ... AZp), that moreover the output of these inverters (lR₁ ... IRp) is in each case connected to one input of an AND-gate (an₁) having p inputs, and that finally the output of this AND-gate (an₁) is provided for the switchover of the counting direction in the reference counter (RZ) from the forwards-counting direction into the opposite counting direction for the duration of a « 1 present at the output of the AND-gate (an₁), and for the control of backwards-counting pulses which are fed to the counting input of the reference counter (RZ) during the backwards-counting phase (Fig. 8).

38. A digital semiconductor circuit as claimed in the claims 35 and 36, characterised in that the circuit section (TLO₁ ... TLOp) which is assigned to the individual age counter (AZ₁ ... AZp) and the supply thereof with counting clock pulses includes an AND-gate having two inputs, that one of these inputs is acted upon by the comparator (K₁ ... Kp) in the output channel (V₁ ... Vp) assigned to the age counter (AZ₁ ... AZp) in question, and the other of these inputs is acted upon by the data input (DE) of the channel selector (KW).

39. A digital semiconductor circuit as claimed in claim 35, characterised in that the circuit section (TL0₁ ... TLOp) which responds on the release of that key in the keyboard (M) which is temporarily assigned to a seized output channel (V₁ ... Vp) with a seized age counter includes an AND-gate (1) and a NOR-gate (2) - each having two inputs - that here one input of each of these two gates, (1,2) is controlled by the data input (DE) of the channel selector (KW), and the other is controlled by the output of the comparator (K₁ ... Kp) which belongs to the assigned output channel (V₁ ... Vp) and is acted upon by this and by the sound address counter (TAZ), that moreover the outputs of the two gates (1, 2) are each connected to an input of an RS-flip-flop (3), and that finally a signal (TLO) which co-controls the AND-gate (UL₁ ... ULp) which switches through the counting clock pulses for the associated age counter can be withdrawn from that output (Q) of the RS-flip-flop (3) which has the count « 1 when a « O » occurs at the output of the AND-gate (1) (Fig. 9).

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