EP0043093B1 - Digital semiconductor circuit for an electronic organ - Google Patents

Digital semiconductor circuit for an electronic organ Download PDF

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Publication number
EP0043093B1
EP0043093B1 EP81104862A EP81104862A EP0043093B1 EP 0043093 B1 EP0043093 B1 EP 0043093B1 EP 81104862 A EP81104862 A EP 81104862A EP 81104862 A EP81104862 A EP 81104862A EP 0043093 B1 EP0043093 B1 EP 0043093B1
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EP
European Patent Office
Prior art keywords
decoder
outputs
output
gates
divider
Prior art date
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Expired
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EP81104862A
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German (de)
French (fr)
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EP0043093A3 (en
EP0043093A2 (en
Inventor
Helmut Rösler
Otto Ing. grad. Mühlbauer
Josef Ing. Grad. Dempf
Klaus-Dieter Dipl.-Phys. Bigall
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Siemens AG
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Siemens AG
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Publication of EP0043093A3 publication Critical patent/EP0043093A3/en
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    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H5/00—Instruments in which the tones are generated by means of electronic generators
    • G10H5/02—Instruments in which the tones are generated by means of electronic generators using generation of basic tones
    • G10H5/06—Instruments in which the tones are generated by means of electronic generators using generation of basic tones tones generated by frequency multiplication or division of a basic tone
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H1/00—Details of electrophonic musical instruments
    • G10H1/18—Selecting circuits
    • G10H1/183—Channel-assigning means for polyphonic instruments
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S84/00—Music
    • Y10S84/23—Electronic gates for tones

Definitions

  • EP-A-30 034 describes a digital semiconductor circuit for an electronic organ with a number of control inputs which correspond to the number of play keys in the manual of the organ and with a number of sound signal inputs which are subjected to periodic electrical oscillations by an oscillator system. in which one control input each is assigned to a game button of the manual and one audio signal input is assigned to one audio frequency, in which an audio signal output is also provided for the application of an electro-acoustic transducer and in which the control signals serving to the control inputs finally correspond to the logic levels "1" and "0" correspond.
  • FIG. 1 it initially seems appropriate to use FIG. 1 to present the parts of the circuit described in the main application that are essential for the present additional invention.
  • a depressed play key in manual M of the organ generates a "1" at the control input E of the semiconductor circuit that is assigned to it individually, while the control input E assigned to a play key that is not actuated maintains the level "0".
  • the clock generator TG supplies a shift register PSW with the clock pulses required for reading out the information formed in the shift register PSW between the individual query cycles.
  • the information in the shift register PSW is fed from the individual game keys of the manual M via the control input E assigned to the relevant key in each case to one of the memory cells provided in the shift register PSW.
  • the order of the game buttons in the manual M corresponds to the order of the memory cells assigned to the individual game buttons in shift register PSW.
  • the information periodically shifted out of the shift register PSW reaches a common switching circuit, the input of which is formed by a so-called channel selector KW.
  • channel selector KW which is described in detail in the main application, there are a number of mutually identical branches, each of which represents a sound channel and which, depending on their number 1 or 2 ... with V I or V 2 etc., ie generally with V; are designated.
  • the respective value of the index "i" gives the number of the relevant channel or of the amplitude shaper AF assigned to it; at.
  • the to act upon the individual amplitude formers AF; serving outputs of channels V; are with AU i and the output of the associated amplitude shaper AF; with AG; designated.
  • Each of the output channels V i is provided on the one hand with the required digital information via the channel selector KW, on the other hand by a sound signal generator TOS and finally by a sound address counter TAZ.
  • This sound address counter takes over the shift clocks used to push out the information from the input shift register PSW as counting pulses during the individual polling cycles.
  • the tone address counter TAZ consists of two parts.
  • the first part consists of four consecutive binary counter stages, which are connected in such a way that they only count to the count "12", in order to be switched back to the initial state "1" when the thirteenth count pulse arrives.
  • the second part of the tone address counter TAZ consists of three consecutive counting stages, which are switched so that the highest count corresponds to the number q of the octaves provided in the manual M.
  • the second part of the counter TAZ receives its counting impulses every time the first part of the counter TAZ changes to the count "1".
  • Each of the channels V i provided leads to an amplitude former AF i , which serves to improve the sound.
  • Fig. 1 only the first two channels V I and V 2 along with the associated amplitude formers AF 1 and AF 2 are drawn.
  • FIG. 2 Further parts of a semiconductor circuit according to EP-A-30 034 which are still essential for the invention can be found in FIG. 2, which must first be dealt with in preparation for the invention.
  • the first memory S in the individual channels which holds the four-bit word forming the sound address within the individual octave, consists of four individual shift register cells, in particular of the quasi-static type, which operate in parallel via the decoder D - a "one-out of twelve decoder"" - be evaluated.
  • the - corresponding to the twelve tone names c, cis, d, dis, etc., having twelve signal outputs - the first decoder D is accordingly one AND gate U I or U 2 Vietnamese or respectively.
  • Each of these AND gates has two inputs, the first of which is connected to one of the inputs of the decoder D and the second is connected to one of the twelve sound inputs TSE of the circuit.
  • the twelve sound signal inputs TSE are each supplied with the levels "1" and "0" by one of the twelve sound frequency outputs of the sound frequency generator TOS in the form of square waves having the respective frequency.
  • the output of each of the AND gates U I to U 12 is connected to an input of a common OR gate 0.
  • the tone frequency supplied by the tone generator TOS via the tone signal input TSE assigned to the relevant decoder output appears at the output of the mentioned OR gate 0 in accordance with the tone corresponding to the pressed play key, the tone, however, always belonging to the highest octave.
  • Each of the outputs of the second decoder D * responsible for the address of the octave is in turn connected to an AND gate U 1 * to Uq * , each of which has two inputs.
  • each of these AND gates U 1 * to U q * is not controlled directly by the audio signal inputs TSE like the AND gates of the first group. Rather, the aforementioned first OR gate 0 and a frequency divider TT connected downstream of it serve to apply the required sound frequencies to the AND gates of the second group.
  • the consisting of q-1 divider stages frequency divider TT receives from the output of the first of it to be processed audio signals OR gate 0, further to the direct impingement of the second input of the first output of the second decoder D * lying first AND gate U 1 * from the second group of AND gates is provided.
  • the remaining AND gates of the second group namely the AND gates U 2 * to Uq * , on the other hand, are connected with their second output to the output of the first divider stage or the second divider stage or Vietnamese or. the (q-1) th divider stage of the frequency divider TT connected.
  • the invention relates to a digital semiconductor circuit for an electronic organ with a number of control inputs applied to the manual corresponding to the number of play keys of the manual of the organ and with a number of sound signal inputs applied by an oscillator system with periodic electrical oscillations, in each of which one control input each Game button of the manual and one sound signal input each is assigned a tone frequency of the highest octave of the organ, at which the control inputs are activated by the game buttons of the Manuals serving control signals correspond to the logic levels "1" and "0", in which the individual control inputs are each assigned to a cell of a clock-controlled shift register PSW operated as a parallel series converter and the signal output of the shift register and the clock pulses provided for its operation Control of a switching circuit provided with the totality of the provided sound signal inputs and with the totality of the switching circuits provided, each controlling an amplitude shaper and also having a smaller number of sound signal outputs than the control inputs, in which two memories are also assigned to each of the sound signal outputs of
  • the number t of divider stages in the frequency divider is at least equal to the number q of octaves provided in the manual of the organ and the number u of AND gates provided in the second group of AND gates is greater than the number q of those in the manual
  • the organ provided octaves is that all the AND gates of the second group also have a third signal input and that at least one control input to be set by the player via a switch to the logic "1" level is finally provided to act on the third signal inputs of these AND gates .
  • the player by actuating the control input in question at level "1" or switching this off, can ensure that the outputs of the second decoder D * are transferred during a first operating state of the control input
  • One AND gate of the second group, assigned to the individual outputs of this decoder, is controlled in the manner shown in EP-A-30 034, while in the second operating state set via the setting switch, the outputs of the second decoder are connected to the outputs of the divider stages of the of the frequency divider FF are summarized that the same outputs of the second decoder D * are now each combined with a divider stage which is assigned to the next lowest octave compared to the first operating state of the control input, so that the same by pressing the octave low re sound is generated.
  • This tone appears at the output of an AND gate from the second group of AND gates which is not in operation in the first operating state, while the AND gates of the second group activated in the first operating state can no longer be activate
  • the invention will now be described with reference to an embodiment shown in FIG. 3.
  • the number q of outputs of the second decoder D * is 5 here, so that 5 octaves are accordingly provided in the manual of the organ.
  • the switching parts according to FIG. 2 only the first OR gate 0, the second OR gate 0 * and the divider TT and the entirety of the required AND gates of the second group are shown in FIG. 3, while circuit parts from Fig. 1 are completely omitted.
  • the individual divider stages FF can, for. B. be given by a toggle flip-flop.
  • the number of AND gates U s + of the second group of AND gates is 15, each of which is equipped with 3 signal inputs in accordance with the invention.
  • the circuit shown in FIG. 3 also has three actuating inputs S 1 or S 2 or S 3 to be set to the logic level "1" by means of a setting switch (not shown).
  • the level “1” can be given by the operating potential V DD , for example, when the circuit is designed using n-channel MOS technology.).
  • the AND gates U 1 +, U 3 + and U 6 + are located at output 1 of the second decoder D * and are accordingly assigned to the game keys belonging to the highest octave in the manual M.
  • the AND gates U 2 + , U 5 + , Ug + are connected to output 2 of the decoder D * assigned to the second highest octave in the manual, and the AND gates U 4 + are connected to output 3 of the decoder D * assigned to the third highest octave , U 8 + and U 12 + and at the decoder output 4 assigned to the fourth highest octave the AND gates U 7 +, U 11 + and U 14 + and at the decoder output 5 assigned to the lowest octave of the manual the AND gates U 10 + , U 13 + and U 15 +.
  • the output of the first OR gate 0 means that only one of the above-mentioned AND gates, namely that at the output 1 of the decoder D * AND gate U 1 + is controlled directly, while the application of the AND gate U 2 + to U 15 + takes place exclusively through the intermediary of the divider TT. This has six stages FF.
  • the AND gates U 2 + and U 3 + are located at the output of the first divider stage, the AND gates U 4 + , U 5 + and U 6 + at the output of the second divider stage, and the AND gates U at the output of the third divider stage 7 + , U 8 + and U 9 + , at the output of the fourth divider stage the AND gates U 10 +, U 11 + and U 12 + and at the output of the fifth divider stage the AND gates U 13 +, U 14 + and am Output of the 6th divider stage the AND gate U 15 +.
  • the first control input S I is used to control the AND gates U 1 +, U 2 + , U 4 + , U 7 + , U 10 +
  • the second control input S 2 is used to control the AND gates U 3 + , U s + , U a + , U 11 +, U 13 + and the third control input S 3 for controlling the AND gates U 6 + , U 9 + , U 12 + , U 14 + and U 15 + with the level logic "1 ".
  • the outputs of the individual AND gates U 1 + to U 15 + are each at an input of the second OR gate 0 * , the output of which forms one of the audio signal outputs AU i each of the channels V i provided in the switching circuit according to FIG. 1 and accordingly serves to control one of the provided amplitude shapers AF i .
  • each of the output channels V i of the circuit shown in FIG. 1 is assigned an expansion circuit according to the invention shown in FIG. 3.
  • the actuating inputs S i with the same number i that is, the actuating inputs S I on the one hand, the actuating inputs S 2 on the other hand and the actuating inputs S 3 in turn are connected to one another, so that they are each subjected to the level "1" by a single assigned actuating switch can be.
  • a control input S i is switched on to level "1” it may be appropriate to bring the other control inputs (eg automatically) to level "0" or to keep them.
  • the five outputs of the decoder D * are each via one of the AND gates U 3 + , U 5 + , U 8 + , U 11 + and U 13 + of the five first divider stages FF of the divider TT combined.
  • the five outputs of the decoder D * are each one of the AND gates U 6 + , U 9 + , U 12 +, U 14 + and U 15 + five last stages FF of the divider TT connected. You can see that there are two additional octaves available that can be played from Manual M.
  • control inputs S 1 , S 2 , S 3 clearly determine which of the sound signals appearing at the output of the first OR gate 0 * or at the outputs of the divider stages FF of the divider TT to the second OR gate 0 * and thus to the output AU i of the channel V i containing the supplementary circuit according to the invention can, when appropriately loaded by the second decoder D * and thus the manual M, pass through.
  • a supplement to a digital semiconductor circuit according to the invention in accordance with EP-A-30 034 can be expanded without difficulty.
  • the output of the first OR gate 0 is only linked to a single output of the decoder D *, namely to the output 1 via a single AND gate U 1 +, which is also controlled by the first control input S 1 .
  • the output of the first divider stage FF is used to apply two AND gates U 2 + and U 3 + , the first of which belongs to the control input S I and the decoder output 2 and the second to the control input S 2 and the decoder output 1.
  • the output of the third divider stage and the outputs of the other divider stages are each linked to the intended control inputs S i and the individual outputs of the second decoder D * in such a way that - with the exception of the output of the last two divider stages - each divider stage has three outputs of the Decoder D can be combined, while such a combination of the penultimate divider stage with only two outputs of the decoder D * and, in the case of the last divider stage, only a linkage with only one output of the decoder D * is possible.
  • the assignment between the individual outputs of the decoder D * and the individual control inputs S i is made in such a way that the number of the decoder output linked to the relevant output of the divider TT is higher, the lower the number i of the link involved input S is. Since only one linkage option is provided in the case of the output of the first OR gate 0 or the last divider stage, it only needs to be pointed out here that the last divider stage with the decoder output bearing the highest number and with the highest number i carrying control input S is linked, whereas in the case of the output of the first OR gate 0, only a link is provided with the control input S I carrying the lowest number i, that is number 1 and the decoder output carrying the lowest number, that is number 1.

Description

In der EP-A-30 034 ist eine digitale Halbleiterschaltung für eine elektronische Orgel mit einer der Anzahl der Spieltasten des Manuals der Orgel entsprechenden Anzahl von über das Manual beaufschlagten Steuereingängen sowie mit einer von einer Oszillatoranlage mit periodischen elektrischen Schwingungen beaufschlagten Anzahl von Tonsignaleingängen beschrieben, bei der je ein Steuereingang je einer Spieltaste des Manuals und je ein Tonsignaleingang je einer Tonfrequenz fest zugeordnet ist, bei der ferner ein Tonsignalausgang für die Beaufschlagung eines elektro-akustischen Wandlers vorgesehen ist und bei der schließlich die zur Beaufschlagung der Steuereingänge dienenden Steuersignale den logischen Pegeln "1" und "0" entsprechen.EP-A-30 034 describes a digital semiconductor circuit for an electronic organ with a number of control inputs which correspond to the number of play keys in the manual of the organ and with a number of sound signal inputs which are subjected to periodic electrical oscillations by an oscillator system. in which one control input each is assigned to a game button of the manual and one audio signal input is assigned to one audio frequency, in which an audio signal output is also provided for the application of an electro-acoustic transducer and in which the control signals serving to the control inputs finally correspond to the logic levels "1" and "0" correspond.

Kennzeichnend für die in der EP-A-30 034 beschriebene Schaltung ist, daß die einzelnen Steuereingänge je einer Zelle eines taktgesteuerten und als Parallel-Serienwandler betriebenen Schieberegisters zugeordnet sind, daß ferner sowohl der Signalausgang des Schieberegisters als auch die für dessen Betrieb vorgesehenen Taktimpulse zur Steuerung einer Vermittlungsanlage dienen, die andererseits mit der Gesamtheit der vorgesehenen Tonsignaleingänge versehen ist, daß außerdem die Anzahl der Tonsignalausgänge niedriger ist als die Anzahl der Steuereingänge sowie jedem der Tonsignalausgänge je ein Amplitudenformer zugeordnet ist und daß schließlich die Ausgänge der Amplitudenformer auf einen elektro-akustischen Wandler geschaltet sind.It is characteristic of the circuit described in EP-A-30 034 that the individual control inputs are each assigned to a cell of a clock-controlled shift register operated as a parallel series converter, and that both the signal output of the shift register and the clock pulses provided for its operation are also used Serve control of a switching system, which on the other hand is provided with the entirety of the provided audio signal inputs, that in addition the number of audio signal outputs is lower than the number of control inputs and each of the audio signal outputs is assigned an amplitude shaper and finally that the outputs of the amplitude shifters are assigned to an electro-acoustic Converters are switched.

Es erscheint zunächst angebracht, anhand der Fig. 1 die für die vorliegende Zusatzerfindung wesentlichen Teile der in der Hauptanmeldung beschriebenen Schaltung vorzustellen.It initially seems appropriate to use FIG. 1 to present the parts of the circuit described in the main application that are essential for the present additional invention.

Eine gedrückte Spieltaste in Manual M der Orgel erzeugt eine "1" an dem ihr individuell zugeordneten Steuereingang E der Halbleiterschaltung, während der einer nicht betätigten Spieltaste zugeordnete Steuereingang E den Pegel "0" behält. Durch den Taktgeber TG ist ein Schieberegister PSW mit den zum Auslesen der zwischen den einzelnen Abfragezyklen in Schieberegister PSW gebildeten Informationen erforderlichen Taktimpulsen versorgt. Die Information in Schieberegister PSW wird von den einzelnen Spieltasten des Manuals M über den der betreffenden Taste jeweils zugeordneten Stuereingang E je einer der im Schieberegister PSW vorgesehenen Speicherzellen zugeführt. Die Reihenfolge der Spieltasten im Manual M entspricht der Reihenfolge der den einzelnen Spieltasten in Schieberegister PSW zugeordneten Speicherzellen.A depressed play key in manual M of the organ generates a "1" at the control input E of the semiconductor circuit that is assigned to it individually, while the control input E assigned to a play key that is not actuated maintains the level "0". The clock generator TG supplies a shift register PSW with the clock pulses required for reading out the information formed in the shift register PSW between the individual query cycles. The information in the shift register PSW is fed from the individual game keys of the manual M via the control input E assigned to the relevant key in each case to one of the memory cells provided in the shift register PSW. The order of the game buttons in the manual M corresponds to the order of the memory cells assigned to the individual game buttons in shift register PSW.

Die periodisch aus dem Schieberegister PSW ausgeschobene Information gelangt in eine gemeinsame Vermittlungsschaltung, deren Eingang durch einen sog. Kanalwähler KW gebildet ist. Von Kanalwähler KW, der in Detail in der Hauptanmeldung beschrieben ist, geht eine Anzahl einander gleicher Abzweigungen aus, die jeweils einen Tonkanal darstellen und die je nach ihrer Nummer 1 bzw. 2... mit VI bzw. V2 usw., d.h. allgemein mit V; bezeichnet sind. Dabei gibt der jeweilige Wert des Index "i" die Nummer des betreffenden Kanals bzw. des ihn jeweils zugeordneten Amplitudenformers AF; an. Die zur Beaufschlagung der einzelnen Amplitudenformer AF; dienenden Ausgänge der Kanäle V; sind mit AUi und der Ausgang des zugehörigen Amplitudenformers AF; mit AG; bezeichnet.The information periodically shifted out of the shift register PSW reaches a common switching circuit, the input of which is formed by a so-called channel selector KW. From channel selector KW, which is described in detail in the main application, there are a number of mutually identical branches, each of which represents a sound channel and which, depending on their number 1 or 2 ... with V I or V 2 etc., ie generally with V; are designated. The respective value of the index "i" gives the number of the relevant channel or of the amplitude shaper AF assigned to it; at. The to act upon the individual amplitude formers AF; serving outputs of channels V; are with AU i and the output of the associated amplitude shaper AF; with AG; designated.

Jeder der Ausgangskanäle Vi ist einerseits über den Kanalwähler KW, andererseits von einen TonsignalerzeugerTOS und schließlich von einem Tonadressenzähler TAZ mit den erforderlichen digitalen Informationen versehen. Dieser Tonadressenzähler übernimmt die zum Ausschieben der Information aus den Eingangsschieberegister PSW dienenden Schiebetakte während der einzelnen Abfragezyklen als Zählimpulse.Each of the output channels V i is provided on the one hand with the required digital information via the channel selector KW, on the other hand by a sound signal generator TOS and finally by a sound address counter TAZ. This sound address counter takes over the shift clocks used to push out the information from the input shift register PSW as counting pulses during the individual polling cycles.

Der Tonadressenzähler TAZ besteht aus zwei Teilen. Der erste Teil besteht aus vier hintereinandergeschalteten binären Zählstufen, die derart geschaltet sind, daß sie nur bis zum Zählstand "12" zählen, um beim Eintreffen des jeweils dreizehnten Zählimpulses wieder in den Ausgangszustand "1" umgeschaltet zu sein. Der zweite Teil des Tonadressenzählers TAZ besteht aus drei hintereinander geschalteten Zählstufen, die so geschaltet sind, daß der höchste Zählstand der Anzahl q der vorgesehenen Oktaven im Manual M entspricht. Der zweite Teil des Zählers TAZ erhält seine Zählimpulse jedesmal dann, wenn der erste Teil des Zählers TAZ in den Zählstand "1" übergeht.The tone address counter TAZ consists of two parts. The first part consists of four consecutive binary counter stages, which are connected in such a way that they only count to the count "12", in order to be switched back to the initial state "1" when the thirteenth count pulse arrives. The second part of the tone address counter TAZ consists of three consecutive counting stages, which are switched so that the highest count corresponds to the number q of the octaves provided in the manual M. The second part of the counter TAZ receives its counting impulses every time the first part of the counter TAZ changes to the count "1".

Zu bemerken ist, daß jedesmal bei der Ausgabe einer "1" aus dem Schieberegister PSW der jeweils zugehörige Zählstand beider Teile des Tonadressenzählers TAZ auskodiert und in je einem der in jedem der Kanäle Vi vorgesehenen Speicher S bezüglich der Tonadresse und in je einem der Speicher S* bezüglich der angespielten Oktave temporär gespeichert wird. Voraussetzung hierfür ist, daß durch den Kanalwähler KW der betreffende Ausgangskanal Vi für die Steuerung durch die vom Schieberegister PSW abgegebene "1" freigegeben ist. Dann wird in Schreib-LeseSpeicher S der Name des Tons der zu der das Schieberegister PSW gerade verlassenden "1" gehörigen Spieltaste und in Schreib-LeseSpeicher S* die Nummer der zugehörigen Oktave - jeweils in Form des gerade vorliegenden Zählstands der beiden Teile des Tonadressenzählers - abgespeichert.It should be noted that each time a "1" is output from the shift register PSW, the respectively associated count of both parts of the sound address counter TAZ is encoded and in one of the memories S provided in each of the channels V i with respect to the sound address and in one of the memories S * is temporarily saved with respect to the played octave. The prerequisite for this is that the relevant output channel V i is released by the channel selector KW for control by the "1" output by the shift register PSW. Then the name of the tone of the game button belonging to the "1" that is just leaving the shift register PSW is stored in read / write memory S and the number of the associated octave in read / write memory S * - in each case in the form of the current count of the two parts of the tone address counter - saved.

Jeder der vorgesehenen Kanäle Vi mündet in je einen Amplitudenformer AFi, der der Klangverbesserung dient. Die Anzahl der insgesamt vorgesehenen Kanäle Vi und Amplitudenformer AF; beträgt z. B. n = 10. In Fig. 1 sind lediglich die beiden ersten Kanäle VI und V2 nebst den zugehörigen Amplitudenformern AF1 und AF2 gezeichnet.Each of the channels V i provided leads to an amplitude former AF i , which serves to improve the sound. The total number of channels V i and amplitude shaper AF; is z. B. n = 10. In Fig. 1, only the first two channels V I and V 2 along with the associated amplitude formers AF 1 and AF 2 are drawn.

Weitere für die Erfindung noch wesentliche Teile einer Halbleiterschaltung gemäß der EP-A-30 034 findet man in Fig. 2, auf die in Vorbereitung auf die Erfindung zunächst noch eingegangen werden muß.Further parts of a semiconductor circuit according to EP-A-30 034 which are still essential for the invention can be found in FIG. 2, which must first be dealt with in preparation for the invention.

Der zur Aufnahme des die Tonadresse innerhalb der einzelnen Oktave bildenden Vier-Bit-Wortes dienende erste Speicher S in den einzelnen Kanälen besteht aus vier einzelnen Schieberegisterzellen insbesondere vom quasistatischen Typ, die im Parallelbetrieb über den Dekodierer D - einem "eins-aus zwölf-Dekoder" - ausgewertet werden. Dem - entsprechend den zwölf Tonnamen c, cis, d, dis, usw. zwölf Signalausgänge aufweisenden - ersten Dekodierer D ist dementsprechend pro Signalausgang je ein UND-Gatter UI bzw. U2.....bzw. U12 zugeordnet, die zusammen eine erste Gruppe von UND-Gattern bilden. Jedes dieser UND-Gatter hat zwei Eingänge, von denen der erste an je einem der Eingänge des Dekodierers D liegt und der zweite mit je einem der zwölf Toneingänge TSE der Schaltung verbunden ist. Die zwölf Tonsignaleingänge TSE werden ihrerseits durch je einen der zwölf Tonfrequenzausgänge des Tonfrequenzgenerators TOS in Gestalt von die jeweilige Frequenz aufweisenden Rechteckschwingungen mit den Pegeln "1" und "0" beaufschlagt. Der Ausgang jedes der UND-Gatter UI bis U12 ist an je einen Eingang eines gemeinsamen ODER-Gatters 0 geschaltet.The first memory S in the individual channels, which holds the four-bit word forming the sound address within the individual octave, consists of four individual shift register cells, in particular of the quasi-static type, which operate in parallel via the decoder D - a "one-out of twelve decoder"" - be evaluated. The - corresponding to the twelve tone names c, cis, d, dis, etc., having twelve signal outputs - the first decoder D is accordingly one AND gate U I or U 2 ..... or respectively. U 12 assigned, which together form a first group of AND gates. Each of these AND gates has two inputs, the first of which is connected to one of the inputs of the decoder D and the second is connected to one of the twelve sound inputs TSE of the circuit. The twelve sound signal inputs TSE are each supplied with the levels "1" and "0" by one of the twelve sound frequency outputs of the sound frequency generator TOS in the form of square waves having the respective frequency. The output of each of the AND gates U I to U 12 is connected to an input of a common OR gate 0.

Bedingt durch den jeweiligen Inhalt des den Dekodierer D beaufschlagenden ersten Speichers S erhält nur einer der zwölf Ausgänge des Dekodierers D eine "1", während die übrigen Ausgänge eine "0" behalten. Dementsprechend erscheint am Ausgang des genannten ODER-Gatters 0 die vom Tongenerator TOS über den dem betreffenden Dekoderausgang zugeordneten Tonsignaleingang TSE gelieferte Tonfrequenz nach Maßgabe des der gedrückten Spieltaste entsprechenden Tons, wobei der Ton jedoch immer zur höchsten Oktave gehört.Due to the respective contents of the first memory S which acts on the decoder D, only one of the twelve outputs of the decoder D receives a "1", while the other outputs retain a "0". Accordingly, the tone frequency supplied by the tone generator TOS via the tone signal input TSE assigned to the relevant decoder output appears at the output of the mentioned OR gate 0 in accordance with the tone corresponding to the pressed play key, the tone, however, always belonging to the highest octave.

Der zweite Speicher S* wird durch ein vom zweiten Teil des Tonadressenzählers TAZ geliefertes und die Nummer der des gedrückte Spieltaste enthaltenden Oktave darstellendes Binärwort beaufschlagt und steuert ebenfalls im Parallelbetrieb einen "1-aus-q-Dekoder" D*, wobei q die Anzahl der in Manual M vorgesehenen Oktaven bedeutet. Ist z. B. q = 6, so ist der Dekodierer D* als "l-aus-6-Dekoder" ausgebildet und hat dann dementsprechend 6 Signalausgänge. Jeder der Ausgänge des für die Adresse der Oktave zuständigen zweiten Dekodierers D* liegt wiederum an je einen UND-Gatter U1* bis Uq*, das jeweils zwei Eingänge aufweits. Der zweite Eingang jedes dieser UND-Gatter U1* bis Uq*, also einer zweiten Gruppe von UND-Gattern, wird nicht unmittelbar wie die UND-Gatter der ersten Gruppe von den Tonsignaleingängen TSE her gesteuert. Vielmehr dient zur Beaufschlagung der UND-Gatter der zweiten Gruppe mit den erforderlichen Tonfrequenzen das genannte erste ODER-Gatter 0 und ein diesem nachgeschalteter Frequenzteiler TT.The second memory S * is acted upon by a binary word supplied by the second part of the sound address counter TAZ and represents the number of the octave containing the pressed game key and also controls a "1-out-of-q decoder" D * in parallel operation, where q is the number of means the octaves provided in Manual M. Is z. B. q = 6, the decoder D * is designed as an "I-out-of-6 decoder" and then has 6 signal outputs accordingly. Each of the outputs of the second decoder D * responsible for the address of the octave is in turn connected to an AND gate U 1 * to Uq * , each of which has two inputs. The second input of each of these AND gates U 1 * to U q *, that is to say a second group of AND gates, is not controlled directly by the audio signal inputs TSE like the AND gates of the first group. Rather, the aforementioned first OR gate 0 and a frequency divider TT connected downstream of it serve to apply the required sound frequencies to the AND gates of the second group.

Der aus q-1 Teilerstufen bestehende Frequenzteiler TT erhält die von ihm zu verarbeitenden Tonsignale vom Ausgang des ersten ODER-Gatters 0, der außerdem zur unmittelbaren Beaufschlagung des zweiten Eingangs des am ersten Ausgang des zweiten Dekodierers D* liegenden ersten UND-Gatters U1* aus der zweiten Gruppe von UND-Gattern vorgesehen ist. Die übrigen UND-Gatter der zweiten Gruppe, nämlich die UND-Gatter U2 * bis Uq* sind hingegen mit ihrem zweiten Ausgang mit dem Ausgang der ersten Teilerstufe bzw. der zweiten Teilerstufe bzw.....bzw. der (q-1)-ten Teilerstufe des Frequenzteilers TT verbunden. Dabei ist die Zuordnung der UND-Gatter U1 * bis Uq* und damit der Ausgänge des zweiten Dekodierers D* zu dem Ausgang des ODER-Gatters 0 bzw. den Ausgängen des Frequenzteilers TT so getroffen, daß bei Beaufschlagung eines dieser UND-Gatter Uj* der zweiten Gruppe genau die der Nummer j der zugehörigen Oktave entsprechende Tonfrequenz, die im übrigen von je einem der UND-Gatter U1 bis U12 eingestellt ist, durchgelassen wird. Sie erscheint dann am Ausgang eines zweiten ODER-Gatters 0*, das durch die Ausgänge der UND-Gatter Uj* der zweiten Gruppe, also der UND-Gatter U1* bis Uq*, beaufschlagt ist.The consisting of q-1 divider stages frequency divider TT receives from the output of the first of it to be processed audio signals OR gate 0, further to the direct impingement of the second input of the first output of the second decoder D * lying first AND gate U 1 * from the second group of AND gates is provided. The remaining AND gates of the second group, namely the AND gates U 2 * to Uq * , on the other hand, are connected with their second output to the output of the first divider stage or the second divider stage or ..... or. the (q-1) th divider stage of the frequency divider TT connected. The assignment of the AND gates U 1 * to Uq * and thus the outputs of the second decoder D * to the output of the OR gate 0 or the outputs of the frequency divider TT is made such that when one of these AND gates U j * of the second group is passed exactly the tone frequency corresponding to the number j of the associated octave, which is otherwise set by one of each of the AND gates U 1 to U 12 . *, So the AND gate U 1 * to Uq, * applied then appears at the output of a second OR gate, the 0 of the second group by the outputs of the AND gates U j *.

Die in der EP-A-30 034 beschriebene Ausgestaltung sieht q Oktaven vor, denen jeweils 12 Spieltasten des Manuals M zugeordnet sind, so daß das Manual 12q Spieltasten aufweist. Ist beispielsweise q = 5, so hat das Manual M dementsprechend 60 Spieltasten, denen dann jeweils genau ein Ton zugeordnet ist.The embodiment described in EP-A-30 034 provides q octaves, to which 12 game keys of manual M are assigned, so that the manual has 12 q game keys. If, for example, q = 5, the manual M accordingly has 60 game keys, each of which is assigned exactly one tone.

Es bereitet keine Schwierigkeiten den Teiler TT zu erweitern, falls eine Erweiterung des Tonumfangs der Orgel beabsichtigt ist. Wesentlich aufwendiger ist eine damit verbundene Erweiterung des Manuals M und der Eingangsteile der Schaltung. Es ist deshalb von Bedeutung, eine Möglichkeit zur Verfügung zu haben, die eine Erweiterung des Tonumfangs erlaubt und die ohne eine solche Erweiterung des Manuals M und der Eingangsteile der Schaltung auskommt. Es ist nun Aufgabe der Erfindung, eine auf einfache Weise realisierbare Erweiterung des Tonumfangs der Orgel anzugeben.It is no problem to extend the divider TT if an expansion of the range of the organ is intended. A related extension of the manual M and the input parts of the circuit is much more complex. It is therefore important to have a possibility available that allows an expansion of the tonal range and that does not require such an extension of the manual M and the input parts of the circuit. It is an object of the invention to provide a simple extension of the range of the organ.

Die Erfindung betrifft eine digitale Halbleiterschaltung für eine elektronische Orgel mit einer der Anzahl der Spieltasten des Manuals der Orgel entsprechenden Anzahl von über das Manual beaufschlagten Steuereingängen sowie mit einer von einer Oszillatoranlage mit periodischen elektrischen Schwingungen beaufschlagten Anzahl von Tonsignaleingängen, bei der je ein Steuereingang je einer Spieltaste des Manuals und je ein Tonsignaleingang je einer Tonfrequenz der höchsten Oktave der Orgel fest zugeordnet ist, bei der die zur Beaufschlagung der Steuereingänge durch die Spieltasten des Manuals dienenden Steuersignale den logischen Pegeln "1" und "0" entsprechen, bei der weiterhin die einzelnen Steuereingänge je einer Zelle eines taktgesteuerten und als Parallel-Serienwandler betriebenen Schieberegisters PSW zugeordnet sind und der Signalausgang des Schieberegisters als auch die für dessen Betrieb vorgesehenen Taktimpulse zur Steuerung einer mit der Gesamtheit der vorgesehenen Tonsignaleingänge sowie mit der Gesamtheit der - je einen Amplitudenformer steuernden sowie eine in Vergleich zu den Steuereingängen in geringerer Anzahl vorhandenen - Tonsignalausgänge versehenen Vermittlungsschaltung vorgesehen sind, bei der ferner jedem der Tonsignalausgänge der Vermittlungsschaltung je zwei Speicher zugeordnet sind und jedem dieser Speicher jeweils ein Dekodierer nachgeschaltet sowie die Gesamtheit der vorgesehenen Amplitudenformer zur Steuerung wenigstens eines elektro-akustischen Wandlers vorgesehen ist, bei der außerdem die über einen von den Schiebetakten des Schieberegisters mit Zählimpulsen versorgten Tonadressenzähler erfolgende Beaufschlagung des den einzelnen Tonsignalausgängen jeweils zugeordneten Speicherpaares derart getroffen ist, daß der erste Speicher und der ihm nachgeschaltete erste Dekodierer der Auswertung des Tonnamens und der zweite Speicher sowie der diesem nachgeschaltete zweite Dekodierer der Auswertung der Oktave der dem betreffenden Tonsignal aufgrund der Wirkung der Vermittlungsschaltung jeweils zugeteilten und vom Manual der Orgel stammenden Toninformation zugeordnet ist, bei der weiterhin jeder der Ausgänge des den einzelnen Tonsignalen jeweils zugeordneten ersten Dekodierers mit je einem der vorgesehenen Tonsignaleingänge und jeder dieser Tonsignaleingänge mit je einem der vorgesehenen Ausgänge des ersten Dekodierers über je ein zu einer ersten Gruppe von UND-Gattern gehörendes UND-Gatter und die Ausgänge der ersten Gruppe von UND-Gattern über ein gemeinsames erstes ODER-Gatter zusammengefaßt sind, und bei der schließlich durch das erste ODER-Gatter ein Frequenzteiler sowie - teils unter Vermittlung dieses Frequenzteilers - eine zweite Gruppe von UND-Gattern gesteuert ist, bei der der zweite Eingang der einzelnen UND-Gatter durch die einzelnen Ausgänge des zweiten Dekodierers beaufschlagt ist.The invention relates to a digital semiconductor circuit for an electronic organ with a number of control inputs applied to the manual corresponding to the number of play keys of the manual of the organ and with a number of sound signal inputs applied by an oscillator system with periodic electrical oscillations, in each of which one control input each Game button of the manual and one sound signal input each is assigned a tone frequency of the highest octave of the organ, at which the control inputs are activated by the game buttons of the Manuals serving control signals correspond to the logic levels "1" and "0", in which the individual control inputs are each assigned to a cell of a clock-controlled shift register PSW operated as a parallel series converter and the signal output of the shift register and the clock pulses provided for its operation Control of a switching circuit provided with the totality of the provided sound signal inputs and with the totality of the switching circuits provided, each controlling an amplitude shaper and also having a smaller number of sound signal outputs than the control inputs, in which two memories are also assigned to each of the sound signal outputs of the switching circuit and each of these memories is followed by a decoder and the entirety of the provided amplitude formers is provided for controlling at least one electro-acoustic transducer, in addition to which one of the shift clocks of the shift control sters supplied with counting impulses, the addressing of the memory pair assigned to the individual audio signal outputs takes place in such a way that the first memory and the first decoder downstream of the evaluation of the audio name and the second memory as well as the second decoder downstream of this evaluating the octave of the audio signal in question due to the effect of the switching circuit, assigned and originating from the manual of the organ, sound information is assigned, in which each of the outputs of the first decoder assigned to the individual sound signals, each with one of the provided sound signal inputs and each of these sound signal inputs, each with one of the intended outputs of the first decoder via an AND gate belonging to a first group of AND gates and the outputs of the first group of AND gates are combined via a common first OR gate, and finally dur ch the first OR gate is a frequency divider and - partly by means of this frequency divider - a second group of AND gates is controlled, in which the second input of the individual AND gates is acted upon by the individual outputs of the second decoder.

Erfindungsgemäß ist dabei vorgesehen, daß die Anzahl t der Teilerstufen im Frequenzteiler mindestens gleich der Anzahl q der im Manual der Orgel vorgesehenen Oktaven sowie die Anzahl u der in der zweiten Gruppe von UND-Gattern vorgesehenen UND-Gatter größer als die Anzahl q der im Manual der Orgel vorgesehenen Oktaven ist, daß außerdem sämtliche UND-Gatter der zweiten Gruppe einen dritten Signaleingang aufweisen und daß schließlich zur Beaufschlagung der dritten Signaleingänge dieser UND-Gatter wenigstens ein vom Spieler über einen Schalter an den Pegel logisch "1" zu legender Stelleingang vorgesehen ist.It is provided according to the invention that the number t of divider stages in the frequency divider is at least equal to the number q of octaves provided in the manual of the organ and the number u of AND gates provided in the second group of AND gates is greater than the number q of those in the manual The organ provided octaves is that all the AND gates of the second group also have a third signal input and that at least one control input to be set by the player via a switch to the logic "1" level is finally provided to act on the third signal inputs of these AND gates .

Durch eine solche Erweiterung der in der Hauptanmeldung beschriebenen Schaltungen kann der Spieler durch Betätigung des den betreffenden Stelleingang an den Pegel "1" legenden bzw. von diesem abschaltenden Stellschalters dafür sorgen, daß während eines ersten Betriebszustands des Stelleingangs die Ausgänge des zweiten Dekodierers D* über je ein den einzelnen Ausgängen dieses Dekodierers jeweils zugeordnetes UND-Gatter der zweiten Gruppe in der aus der EP-A-30 034 ersichtlichen Weise gesteuert werden, während beim zweiten über den Stellschalter eingestellten Betriebszustand die Ausgänge des zweiten Dekodierers derart mit den Ausgängen der Teilerstufen des des Frequenzteilers FF zusammengefaßt sind, daß dieselben Ausgänge des zweiten Dekodierers D* nunmehr jeweils mit einer Teilerstufe zusammengefaßt sind, die der jeweils nächst niedrigen Oktave im Vergleich zum ersten Betriebszustand des Stelleingangs zugeordnet ist, so daß durch dieselbe Spieltaste jeweils der um eine Oktave niedrigere Ton erzeugt wird. Dieser Ton erscheint am Ausgang eines beim ersten Betriebszustand nicht in Tätigkeit befindlichen UND-Gatters aus der zweiten Gruppe von UND-Gattern, während die beim ersten Betriebszustand aktivierten UND-Gatter der zweiten Gruppe nunmehr durch den zweiten Dekodierer D* nicht mehr aktivierbar sind.Through such an expansion of the circuits described in the main application, the player, by actuating the control input in question at level "1" or switching this off, can ensure that the outputs of the second decoder D * are transferred during a first operating state of the control input One AND gate of the second group, assigned to the individual outputs of this decoder, is controlled in the manner shown in EP-A-30 034, while in the second operating state set via the setting switch, the outputs of the second decoder are connected to the outputs of the divider stages of the of the frequency divider FF are summarized that the same outputs of the second decoder D * are now each combined with a divider stage which is assigned to the next lowest octave compared to the first operating state of the control input, so that the same by pressing the octave low re sound is generated. This tone appears at the output of an AND gate from the second group of AND gates which is not in operation in the first operating state, while the AND gates of the second group activated in the first operating state can no longer be activated by the second decoder D * .

Die soeben beschriebene Möglichkeit beim Betrieb einer der Erfindung entsprechenden Schaltung ist bereits dann gegeben, wenn die Zahl der Teilerstufen im Teiler TT gleich der Anzahl q der in Manual der Orgel vorgesehenen Oktaven und damit gleich der Anzahl der Ausgänge des zweiten Dekodierers D* ist. Ist die Anzahl der Teilerstufen noch größer, so gelingt es ohne Schwierigkeiten und größerem Aufwand die Schaltung derart auszugestalten, daß die Beaufschlagung durch das Manual M um zwei oder mehr Oktaven in Richtung niedrigerer Tonhöhe nach Belieben verschoben werden kann. Indem man den jeweils einem der vorgesehenen Stelleingänge zugeordneten Stellschalter in Gestalt eines Kippschalters am Spieltisch der Orgel neben dem Manual vorsieht, kann eine solche Verschiebung ohne weiteres auch während des Spielens vorgenommen werden.The possibility just described when operating a circuit according to the invention is already given when the number of divider stages in the divider TT is equal to the number q of the octaves provided in the organ manual and thus to the number of outputs of the second decoder D * . If the number of divider stages is even greater, the circuit can be designed in such a way that the loading by the manual M can be shifted by two or more octaves towards the lower pitch at will. By providing the control switch in the form of a toggle switch on the game table of the organ next to the manual, which is assigned to one of the intended control inputs, such a shift can easily be carried out even while playing.

Die Erfindung wird nun anhand eines in Fig. 3 dargestellten Ausführungsbeispiels näher beschrieben. Die Anzahl q der Ausgänge des zweiten Dekoders D* ist hier gleich 5, so daß dementsprechend im Manual der Orgel 5 Oktaven vorgesehen sind. Von den Schaltteilen gemäß Fig. 2 ist in Fig. 3 nur das erste ODER-Gatter 0, das zweite ODER-Gatter 0* sowie der Teiler TT und die Gesamtheit der erforderlichen UND-Gatter der zweiten Gruppe dargestellt, während Schaltungsteile aus Fig. 1 vollständig weggelassen sind.The invention will now be described with reference to an embodiment shown in FIG. 3. The number q of outputs of the second decoder D * is 5 here, so that 5 octaves are accordingly provided in the manual of the organ. Of the switching parts according to FIG. 2, only the first OR gate 0, the second OR gate 0 * and the divider TT and the entirety of the required AND gates of the second group are shown in FIG. 3, while circuit parts from Fig. 1 are completely omitted.

Die Anzahl der Teilerstufen FF ist im den gezeichneten Beispielsfall durch t = 6 gegeben, so daß zusammen mit dem Ausgang des ersten ODER-Gatters sieben Anschlüsse zur Verfügung stehen, die jeweils die Tonfrequenzen je einer Oktave liefern, so daß insgesamt 7 Oktaven zur Verfügung stehen, obwohl im Manual M der Orgel nur die Spieltasten für 5 Oktaven zur Verfügung stehen. Die einzelnen Teilerstufen FF können z. B. durch je ein Toggle-Flip-Flop gegeben sein. Die Anzahl der UND-Gatter Us + der zweiten Gruppe von UND-Gattern beträgt 15, die entsprechen der Erfindung mit jeweils 3 Signaleingängen ausgestattet sind.The number of divider stages FF in the example shown is given by t = 6, so that together with the output of the first OR gate there are seven connections available, each of which provides the sound frequencies of one octave, so that a total of 7 octaves are available , although only manual keys for 5 octaves are available in Manual M of the organ. The individual divider stages FF can, for. B. be given by a toggle flip-flop. The number of AND gates U s + of the second group of AND gates is 15, each of which is equipped with 3 signal inputs in accordance with the invention.

Die in Fig. 3 dargestellte Schaltung hat außerdem drei durch je einen (nicht gezeichneten) Stellschalter an den Pegel logisch "1" zu legende Stelleingänge S1 bzw. S2 bzw. S3. (Der Pegel "1" kann z. B. bei Ausgestaltung der Schaltung in n-Kanal-MOS-Technik durch das Betriebspotenial VDD gegeben sein.). Für die einzelnen UND-Gatter U1 + bis U15 + hat man die aus Fig. 3 ersichtliche Anschaltung.The circuit shown in FIG. 3 also has three actuating inputs S 1 or S 2 or S 3 to be set to the logic level "1" by means of a setting switch (not shown). (The level "1" can be given by the operating potential V DD , for example, when the circuit is designed using n-channel MOS technology.). For the individual AND gates U 1 + to U 15 + one has the connection shown in FIG. 3.

Die UND-Gatter U1+, U3 + und U6 + liegen am Ausgang 1 des zweiten Dekodierers D* und sind dementsprechend den zu der höchsten Oktave im Manual M gehörenden Spieltasten zugeordnet. An den der zweithöchsten Oktave im Manual zugeordneten Ausgang 2 des Dekodierers D* liegen die UND-Gatter U2 +, U5 +, Ug+, an den der dritthöchsten Oktave zugeordneten Ausgang 3 des Dekoders D* liegen die UND-Gatter U4 +, U8 + und U12+ und an dem der vierthöchsten Oktave zugeordneten Dekoderausgang 4 die UND-Gatter U7+, U11 + und U14 + sowie an dem der niedrigsten Oktave des Manuals zugeordneten Dekoderausgang 5 die UND-Gatter U10 +, U13 + und U15+.The AND gates U 1 +, U 3 + and U 6 + are located at output 1 of the second decoder D * and are accordingly assigned to the game keys belonging to the highest octave in the manual M. The AND gates U 2 + , U 5 + , Ug + are connected to output 2 of the decoder D * assigned to the second highest octave in the manual, and the AND gates U 4 + are connected to output 3 of the decoder D * assigned to the third highest octave , U 8 + and U 12 + and at the decoder output 4 assigned to the fourth highest octave the AND gates U 7 +, U 11 + and U 14 + and at the decoder output 5 assigned to the lowest octave of the manual the AND gates U 10 + , U 13 + and U 15 +.

Hinsichtlich der Versorgung der genannten 15 UND-Gatter U1+ bis U15+ mit Tonfrequenzen ist festzustellen, daß durch den Ausgang des ersten ODER-Gatters 0 nur ein einziges der genannten UND-Gatter, nämlich das am Ausgang 1 des Dekodierers D* liegende UND-Gatter U1+ unmittelbar gesteuert wird, während die Beaufschlagung der UND-Gatter U2 + bis U15+ ausschließlich unter Vermittlung des Teilers TT erfolgt. Dieser hat sechs Teilerstufen FF.With regard to the supply of the above-mentioned 15 AND gates U 1 + to U 15 + with sound frequencies, it should be noted that the output of the first OR gate 0 means that only one of the above-mentioned AND gates, namely that at the output 1 of the decoder D * AND gate U 1 + is controlled directly, while the application of the AND gate U 2 + to U 15 + takes place exclusively through the intermediary of the divider TT. This has six stages FF.

Dabei liegen am Ausgang der ersten Teilerstufe die UND-Gatter U2 + und U3 +, am Ausgang der zweiten Teilerstufe die UND-Gatter U4 +, U5 + und U6 +, am Ausgang der dritten Teilerstufe die UND-Gatter U7 +, U8+ und U9 +, am Ausgang der vierten Teilerstufe die UND-Gatter U10+, U11 + und U12 + sowie am Ausgang der fünften Teilerstufe die UND-Gatter U13+, U14 + und am Ausgang der 6. Teilerstufe das UND-Gatter U15+.The AND gates U 2 + and U 3 + are located at the output of the first divider stage, the AND gates U 4 + , U 5 + and U 6 + at the output of the second divider stage, and the AND gates U at the output of the third divider stage 7 + , U 8 + and U 9 + , at the output of the fourth divider stage the AND gates U 10 +, U 11 + and U 12 + and at the output of the fifth divider stage the AND gates U 13 +, U 14 + and am Output of the 6th divider stage the AND gate U 15 +.

Schließlich dient der erste Stelleingang SI zur Steuerung der UND-Gatter U1+, U2 +, U4 +, U7 +, U10+, der zweite Stelleingang S2 zur Steuerung der UND-Gatter U3 +, Us +, Ua +, U11+, U13 + und der dritte Stelleingang S3 zur Steuerung der UND-Gatter U6 +, U9 +, U12 +, U14+ und U15+ mit dem Pegel logisch "1".Finally, the first control input S I is used to control the AND gates U 1 +, U 2 + , U 4 + , U 7 + , U 10 +, the second control input S 2 is used to control the AND gates U 3 + , U s + , U a + , U 11 +, U 13 + and the third control input S 3 for controlling the AND gates U 6 + , U 9 + , U 12 + , U 14 + and U 15 + with the level logic "1 ".

Die Ausgänge der einzelnen UND-Gatter U1 + bis U15 + liegen an je einem Eingang des zweiten ODER-Gatters 0* , dessen Ausgang einen der Tonsignalausgänge AUi je eines der vorgesehenen Kanäle Vi in der Vermittlungsschaltung entsprechend Fig. 1 bildet und demgemäß zur Steuerung eines der vorgesehenen Amplitudenformer AFi dient.The outputs of the individual AND gates U 1 + to U 15 + are each at an input of the second OR gate 0 * , the output of which forms one of the audio signal outputs AU i each of the channels V i provided in the switching circuit according to FIG. 1 and accordingly serves to control one of the provided amplitude shapers AF i .

Zu bemerken ist, daß jedem der Ausgangskanäle Vi der in Fig. 1 ersichtlichen Schaltung je eine in Fig. 3 dargestellte Erweiterungsschaltung gemäß der Erfindung zugeordnet ist. Dabei sind jedoch die Stelleingänge Si mit gleicher Numner i, also die Stelleingänge SI einerseits, die Stelleingänge S2 andererseits und die Stelleingänge S3 ihrerseits miteinander verbunden, so daß sie jeweils durch einen einzigen zugeordneten Stellschalter gemeinsam mit dem Pegel "1" beaufschlagt werden können. Zu bemerken ist außerdem, daß es beim Einschalten eines Stelleingangs Si auf den Pegel "1" ggf. angebracht sein kann, die restlichen Stelleingänge (z. B. automatisch) auf den Pegel "0" zu bringen bzw. zu halten.It should be noted that each of the output channels V i of the circuit shown in FIG. 1 is assigned an expansion circuit according to the invention shown in FIG. 3. However, the actuating inputs S i with the same number i, that is, the actuating inputs S I on the one hand, the actuating inputs S 2 on the other hand and the actuating inputs S 3 in turn are connected to one another, so that they are each subjected to the level "1" by a single assigned actuating switch can be. It should also be noted that when a control input S i is switched on to level "1" it may be appropriate to bring the other control inputs (eg automatically) to level "0" or to keep them.

Die Wirkung der Schaltung gemäß Fig. 3 wird unmittelbar beim Betrachten der Figur verständlich. Liegt am Stelleingang SI eine "1" und an den beiden anderen Stelleingängen S2 und S3 der Pegel "0", dann sind die fünf Ausgänge 1 - 5 des zweiten Dekodierers D* über je eines der UND-Gatter U1+, U2 +, U4 +, U7 + und Ulo + mit dem Ausgang des ersten ODER-Gatters 0 bzw. dem Ausgang je einer der vier ersten Teilerstufen FF des Teilers TT verknüpft, so daß bei Betätigung des Manuals M die Töne der fünf höchsten Oktaven geliefert werden. Liegt hingegen am Stelleingang S2 der Pegel "1", dann sind die fünf Ausgänge des Dekodierers D* über je eines der UND-Gatter U3 +, U5 +, U8 +, U11+ und U13 + mit je einer der fünf ersten Teilerstufen FF des Teilers TT kombiniert. Liegt schließlich am Stelleingang S3 der Pegel "1" dann sind die fünf Ausgänge des Dekodierers D* über je eines der UND-Gatter U6 +, U9 +, U12+, U14 + und U15 + an je eine der fünf letzten Stufen FF des Teilers TT angeschlossen. Mann erkennt somit, daß man zwei zusätzliche Oktaven zur Verfügung hat, die vom Manual M aus gespielt werden können. Über die Stelleingänge S1, S2, S3 wird ersichtlich bestimmt, welche der am Ausgang des ersten ODER-Gatters 0* bzw. an den Ausgängen der Teilerstufen FF des Teilers TT erscheinenden Tonsignale an das zweite ODER-Gatter 0* und damit an den Ausgang AUi des die erfindungsgemäße Ergänzungsschaltung enthaltenden Kanals Vi bei entsprechender Beaufschlagung durch den zweiten Dekodierer D* und damit des Manuals M gelangen können.The effect of the circuit according to FIG. 3 is immediately understandable when looking at the figure. If there is a "1" at the control input S I and the level "0" at the two other control inputs S 2 and S 3 , then the five outputs 1 - 5 of the second decoder D * are each via one of the AND gates U 1 +, U 2 + , U 4 + , U 7 + and U lo + with the output of the first OR gate 0 or the output of one of the four first divider stages FF of the divider TT, so that when the manual M is pressed, the tones of the five highest octaves. However, if the level "1" is at the control input S 2 , then the five outputs of the decoder D * are each via one of the AND gates U 3 + , U 5 + , U 8 + , U 11 + and U 13 + of the five first divider stages FF of the divider TT combined. Finally, if the level "1" is at the control input S 3 , the five outputs of the decoder D * are each one of the AND gates U 6 + , U 9 + , U 12 +, U 14 + and U 15 + five last stages FF of the divider TT connected. You can see that there are two additional octaves available that can be played from Manual M. The control inputs S 1 , S 2 , S 3 clearly determine which of the sound signals appearing at the output of the first OR gate 0 * or at the outputs of the divider stages FF of the divider TT to the second OR gate 0 * and thus to the output AU i of the channel V i containing the supplementary circuit according to the invention can, when appropriately loaded by the second decoder D * and thus the manual M, pass through.

Eine der Erfindung entsprechende Ergänzung einer digitalen Halbleiterschaltung gemäß der EP-A-30 034 läßt sich ohne Schwierigkeiten erweitern.A supplement to a digital semiconductor circuit according to the invention in accordance with EP-A-30 034 can be expanded without difficulty.

Im allgemeinen wird die Anzahl der UND-Gatter Us + gleich dem Produkt aus der Gesamtzahl der Ausgänge q des zweiten Dekodierers D* mit der Gesamtzahl p der Stelleingänge S gewählt werden, wobei die jeweils dieselbe Anzahl von UND-Gattern Us + an den einzelnen Stelleingang angelegt ist. Ferner ist die Anzahl p der Stelleingänge S auf die Anzahl t der vorgesehenen Teilerstufen FF des Frequenzteilers TT derart abgestimnt, daß (t + 1 - q) = (p 1) gilt. Ferner ist dabei jedem der q Ausgänge des zweiten Dekodierers D* jeweils dieselbe Anzahl u : q von UND-Gattern der zweiten Gruppe zugeordnet, wobei u die Gesamtzahl dieser UND-Gatter ist.In general, the number of AND Gates U s + equal to the product of the total number of outputs q of the second decoder D * with the total number p of control inputs S are selected, the same number of AND gates U s + being applied to the individual control input. Furthermore, the number p of the control inputs S is matched to the number t of the intended divider stages FF of the frequency divider TT such that (t + 1 - q) = (p 1) applies. Furthermore, each of the q outputs of the second decoder D * is assigned the same number u: q of AND gates of the second group, u being the total number of these AND gates.

Bezüglich der Verknüpfung der Ausgänge des zweiten Dekodierers D* mit dem Ausgang des ersten ODER-Gatters 0 bzw. der einzelnen Ausgänge des Frequenzteilers TT wird man im Einklang mit der in Fig. 3 dargestellten Schaltung darauf achten, daß ungeachtet der jeweiligen Einstellung durch die Stelleingänge Si immer beim Erscheinen einer "1" an jedem der Ausgänge des Dekodierers D* an den Ausgang des zweiten ODER-Gatters 0* ein Tonsignal gelangt, dessen Frequenz umso niedriger ist je höher die Nummer des betreffenden Dekoderausgangs und damit umso niedriger die dem betreffenden Dekoderausgang zugeordnete Frequenz im Manual M ist und je höher die Nummer i des das Erscheinen des Tonsignals ermöglichenden Stelleingang Si ist.Regarding the combination of the outputs of the second decoder D * with the output of the first OR gate 0 or the individual outputs of the frequency divider TT, one will take care in accordance with the circuit shown in FIG. 3 that regardless of the respective setting by the control inputs S i whenever a "1" appears at each of the outputs of the decoder D * at the output of the second OR gate 0 * a sound signal whose frequency is lower, the higher the number of the decoder output in question and thus the lower the number of the relevant one Frequency assigned to the decoder output in the manual M is and the higher the number i of the control input S i which enables the sound signal to appear.

Um das zu erreichen, wird der Ausgang des ersten ODER-Gatters 0 lediglich mit einem einzigen Ausgang des Dekodierers D*, nämlich mit dem Ausgang 1 über ein einziges UND-Gatter U1 + verknüpft, das durch den ersten Stelleingang S1 mitgesteuert ist. Ferner dient der Ausgang der ersten Teilerstufe FF zur Beaufschlagung zweier UND-Gatter U2+ und U3 +, von denen das erste zum Stelleingang SI und zum Dekoderausgang 2 und das zweite zum Stelleingang S2 und zum Dekoderausgang 1 gehört. Der Ausgang der dritten Teilerstufe und die Ausgänge der übrigen Teilerstufen sind jeweils mit den vorgesehenen Stelleingängen Si und den einzelnen Ausgängen des zweiten Dekodierers D* so verknüpft, daß - mit Ausnahme des Ausgangs der beiden letzten Teilerstufen - daß jede Teilerstufe jeweils mit drei Ausgängen des Dekodierers D kombinierbar ist, während eine solche Kombination der vorletzten Teilerstufe mit nur zwei Ausgängen des Dekodierers D* und im Falle der letzten Teilerstufe nur eine Verknüpfung nur mit einem Ausgang des Dekodierers D* möglich ist. Dabei ist bei allen Verknüpfungen die Zuordnung zwischen den einzelnen Ausgängen des Dekodierers D* und den einzelnen Stelleingängen Si so getroffen, daß die Nummer des mit dem betreffenden Ausgang des Teilers TT verknüpften Dekoderausgangs umso höher ist, je niedriger die Nummer i des bei der Verknüpfung beteiligten Stelleingangs S ist. Da im Falle des Ausgangs des ersten ODER-Gatters 0 bzw. der letzten Teilerstufe jeweils nur eine Verknüpfungsmöglichkeit vorgesehen ist, braucht hier nur noch darauf hingewiesen zu werden, daß die letzte Teilerstufe mit dem die höchste Nummer tragenden Dekoderausgang sowie mit dem die höchste Nummer i tragenden Stelleingang S verknüpft ist, während im Falle des Ausgangs des ersten ODER-Gatters 0 nur eine Verknüpfung mit dem die niedrigste Nummer i, also die Nummer 1 tragenden Stelleingang SI und dem die niedrigste Nummer, also die Nummer 1 tragenden Dekoderausgang vorgesehen ist. Zu bemerken ist schließlich, daß die Zusammenfassung der einzelnen Ausgänge des Teilers TT mit den einzelnen Ausgängen des Dekodierers D* so getroffen ist, daß die mit dem Ausgang jeder der Teilerstufen verknüpfbaren Ausgänge des Dekodierers D* ausschließlich unmittelbar aufeinanderfolgenden Oktaven des Manuals M zugeordnet sind und damit eine fortlaufend nummerierte Zahlenreihe bilden. Diese Betrachtungen gelten auch für eine Erweiterung der in Fig. 3 dargestellten Schaltung auf mehr als 6 Teilerstufen FF und mehr als 5 Ausgängen des Dekoders D*.To achieve this, the output of the first OR gate 0 is only linked to a single output of the decoder D *, namely to the output 1 via a single AND gate U 1 +, which is also controlled by the first control input S 1 . Furthermore, the output of the first divider stage FF is used to apply two AND gates U 2 + and U 3 + , the first of which belongs to the control input S I and the decoder output 2 and the second to the control input S 2 and the decoder output 1. The output of the third divider stage and the outputs of the other divider stages are each linked to the intended control inputs S i and the individual outputs of the second decoder D * in such a way that - with the exception of the output of the last two divider stages - each divider stage has three outputs of the Decoder D can be combined, while such a combination of the penultimate divider stage with only two outputs of the decoder D * and, in the case of the last divider stage, only a linkage with only one output of the decoder D * is possible. The assignment between the individual outputs of the decoder D * and the individual control inputs S i is made in such a way that the number of the decoder output linked to the relevant output of the divider TT is higher, the lower the number i of the link involved input S is. Since only one linkage option is provided in the case of the output of the first OR gate 0 or the last divider stage, it only needs to be pointed out here that the last divider stage with the decoder output bearing the highest number and with the highest number i carrying control input S is linked, whereas in the case of the output of the first OR gate 0, only a link is provided with the control input S I carrying the lowest number i, that is number 1 and the decoder output carrying the lowest number, that is number 1. Finally, it should be noted that the combination of the individual outputs of the divider TT with the individual outputs of the decoder D * is such that the outputs of the decoder D * which can be linked to the output of each of the divider stages are exclusively assigned to immediately successive octaves of the manual M and to form a consecutively numbered series of numbers. These considerations also apply to an expansion of the circuit shown in FIG. 3 to more than 6 divider stages FF and more than 5 outputs of the decoder D * .

Unabhängig von einer entsprechend der Erfindung ausgestalteten Ergänzungsschaltung bestehen noch weitere Möglichkeiten zur Erweiterung des Tonbereichs der eine Schaltung gemäß der EP-A-30 034 verwendenden elektronischen Orgel. So könnte man z. B. den Dekodierer D* vergrößern und die Oktavadresse vor der Dekodierung umrechnen, d.h. eine Konstante hinzu zu zählen. Man könnte auch den Tonadressenzähler TAZ z. B. unter Verwendung eines Presets (statt eines Resets) mit dieser Konstanten voreinstellen. Schließlich gibt es noch die Möglichkeit, zwischen dem Ausgang des ersten ODER-Gatters 0 und dem Eingang des - entsprechend erweiterten Frequenzteilers TT - eine durch Stellschalter zu steuernde Weiche zu legen, derart, daß je nach Stellung der Weiche verschiedene Tonfrequenzen an die in der EP-A-30 034 beschriebenen und in Fig. 2 dargestellten UND-Gatter U1* bis Uq* gelangen. Jedoch dürfte die oben und anhand von Fig. 3 beschriebene Möglichkeit die optimale Lösung brigen.Regardless of a supplementary circuit designed in accordance with the invention, there are further possibilities for expanding the tone range of the electronic organ using a circuit according to EP-A-30 034. So you could e.g. B. enlarge the decoder D * and convert the octave address before decoding, ie to add a constant. You could also use the sound address counter TAZ z. B. use a preset (instead of a reset) to preset these constants. Finally, there is also the possibility of placing a crossover to be controlled by a setting switch between the output of the first OR gate 0 and the input of the - correspondingly expanded frequency divider TT, such that, depending on the position of the crossover, different sound frequencies to those in the EP -A-30 034 and shown in Fig. 2 AND gates U 1 * to Uq * arrive. However, the possibility described above and with reference to FIG. 3 should bring the optimal solution.

Claims (6)

1. A digital semiconductor circuit for an electronic organ comprising a number, corresponding to the number of keys of the organ keyboard, of control inputs which are acted upon via the keyboard, and with a number of sound signal inputs which are supplied by an oscillator system with periodic, electrical oscillations, where each control input is permanently assigned to a key of the keyboard and each sound signal input is permanently assigned to a sound frequency of the highest octave of the organ, where the control signals, which act upon the control inputs via the keys of the keyboard, correspond to logic levels "1" and "0", where moreover the individual control inputs are each assigned to one cell of a clock- controlled shift register operated as a parallel- series converter and where both the signal output of the shift register and the clock pulses provided for the operation thereof serve to control a switching circuit which is provided with all the provided sound signal inputs and with all the sound signal outputs - which each control an amplitude shaper and the number of which is smaller than that of the control inputs, where moreover each of the sound signal outputs of the switching circuit is assigned to two stores, each of these stores being followed by a decoder, and where all the provided amplitude shapers serve to control at least one electro-acoustic transducer, where moreover the control of the pair of stores, permanently assigned to the individual sound signal outputs, via a sound address counter which is supplied with counting pulses by the shift clock signals of the shift register is contrived to be such that the first store and the first decoder, connected to its output end, are assigned to the analysis of the sound name, whilst the second store and the second decoder, connected to the output thereof, are assigned to the analysis of the octave of the sound information which is assigned to the respective sound signal via the switching circuit and which originates from the organ keyboard, where moreover each of the outputs of the first decoder, which is assigned to the individual sound signals, is combined with one of the provided sound signal inputs, and each of these sound signal inputs is combined with one of the provided outputs of the first decoder in each case via an AND-gate, assigned to a first group of AND-gates, and where the outputs of the first group of AND-gates are combined via a common, first OR-gate, and where finally the first OR-gate controls a frequency divider and - in part via this frequency divider - a second group of AND-gates, where the second input of the individual AND-gates is connected to the individual outputs of the second decoder, characterised in that the number t of divider stages (FF) in the frequency divider (TT) is at least equal to the number q of octaves provided in the organ keyboard (M) and the number u of AND-gates (Us+) provided in the second group of AND-gates (Us+) is greater than the number q of octaves provided in the organ keyboard (M), that moreover all the AND-gates (Us+) of the second group have a third signal input, and that finally, for the control of the third signal inputs of these AND-gates (Us+) at least one setting input (S;) is provided which is to be connected to the logic "1" level.
2. A semiconductor circuit as claimed in claim 1, characterised in that the number u of the AND-gates (Us+) of the second group is equal to the product of the total number q of outputs of the second decoder (D*) and the total p of setting inputs (Si), that moreover the same number of these AND-gates (Us+) is connected to each of the setting inputs (S;), and that finally the number p of the setting inputs (S;) is adapted to the number t of provided divider stages (FF) in the frequency divider (TT) in such manner that p - 2 = t - q and that moreover each of the q outputs of the second decoder (D*) is assigned the same number u : q of AND-gates (Us+) of the second group.
3. A semiconductor circuit as claimed in claim 1 or 2, characterised in that the logic-linking of the outputs of the first OR-gate (0) and of the divider stages (FF) of the frequency divider (TT) to the individual outputs of the second decoder (D*) and the individual setting inputs (S;) by the provided AND-gates (Us+) of the second group is contrived to be such that when a "1" appears at one of the outputs (1-5) of the decoder (D*), the output of the second OR-gate (0*), which is controlled by the outputs of all the AND-gates (U,+) of the second group, is supplied with a sound signal whose frequency is lower the higher the number of the respective decoder output (1-5) and the higher the number (i) of the setting input (S;) which enables the sound signal to appear.
4. A semiconductor circuit as claimed in claim 2 and 3, characterised in that the output of the first OR-gate (0) is logic-linked only to that output (1) of the second decoder (D*) which is assigned to the highest octave in the keyboard (M), and to the setting input (S1) which has the lowest number, and the output of the last divider stage (FF) of the frequency divider (TT) is logic-linked only to that output (5) of the second decoder (D*) which is assigned to the lowest octave in the keyboard (M), and to the setting input (S3) which has the highest number, that moreover the output of the first divider stage (FF) in the frequency divider (TT) and the output of the last but one divider stage (FF) of the frequency divider (TT) are each logic-linked to two outputs of the second decoder (D*) and to two setting inputs, whilst the outputs of the remaining divider stages (FF) of the divider (TT) are each logic-linked to three outputs of the second decoder (D*), and to three setting inputs (S;), where in each case only one single AND-gate (U,+) of the second group is arranged between in each case one of the decoder outputs (1-5) and in each case one of the participating setting inputs (Si ) and the output of the respective divider stage (FF), that moreover the assignment between the individual outputs (1-5) of the decoder (D*) and the setting inputs (S;) which participate in the respective logic-link, is selected to be such that the number of the decoder output which is logic-linked to the respective output of the divider (TT) is the higher - and thus that octave of the keyboard (M) assigned to the respective decoder output is the lower, the higher the number (i) of the setting input (S;) logic-linked thereto, and that finally those outputs of the second decoder which are AND- logic-linked to the output of the respective divider stage are each assigned to a related series of octaves in the keyboard (M) which are the lower, the further the respective divider stage is located from that input of the divider (TT) which is acted upon by the second OR-gate (0).
5. A semiconductor circuit as claimed in one of the claims 1 to 4, characterised in that the logic- links, in each case formed by an AND-gate (Us+) of the second group, between the outputs of the individual divider stages (FF) and the individual outputs of the second decoder (D*) and the provided setting inputs (S;) all differ from one another, and that the provided setting inputs (S;) can be used individually and in combination.
6. A semiconductor circuit as claimed in one of the claims 1 to 5, characterised in that the provided setting inputs (S;) are simultaneously assigned to a plurality of circuit components which are identical to one another and which each comprise a first and second store (S, S*), a first and second decoder (D, D*), a frequency divider, a first group and second group of AND-gates, and a first and second OR-gate, and that the respective output of the second OR-gate (0) is identical to the sound signal output (AU) of one of the provided channels (V;) of the switching circuit.
EP81104862A 1980-07-01 1981-06-23 Digital semiconductor circuit for an electronic organ Expired EP0043093B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19803024931 DE3024931A1 (en) 1980-07-01 1980-07-01 DIGITAL SEMICONDUCTOR CIRCUIT FOR AN ELECTRONIC ORGAN
DE3024931 1980-07-01

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EP0043093A2 EP0043093A2 (en) 1982-01-06
EP0043093A3 EP0043093A3 (en) 1985-05-02
EP0043093B1 true EP0043093B1 (en) 1988-01-13

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EP (1) EP0043093B1 (en)
JP (1) JPS5744198A (en)
DE (2) DE3024931A1 (en)

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DE102007060144A1 (en) * 2007-12-13 2009-06-18 Alexander Koslow Device for separating heavy and light materials of a pre-crushed mixture of waste material comprises a filling shaft for passing the waste material to a flow channel at an angle which is directed vertical to the channel
IL224642A (en) 2013-02-10 2015-01-29 Ronen Lifshitz Modular electronic musical keyboard instrument
CN108648738B (en) * 2018-06-26 2023-05-30 宗仁科技(平潭)有限公司 Integrated circuit of electronic organ

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JPS5123337B2 (en) * 1972-05-24 1976-07-16
US4016495A (en) * 1974-06-03 1977-04-05 The Wurlitzer Company Electronic musical instrument using plural programmable divider circuits
US4019417A (en) * 1974-06-24 1977-04-26 Warwick Electronics Inc. Electrical musical instrument with chord generation

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DE3024931A1 (en) 1982-01-28
EP0043093A3 (en) 1985-05-02
EP0043093A2 (en) 1982-01-06
US4428267A (en) 1984-01-31
JPS5744198A (en) 1982-03-12
DE3176614D1 (en) 1988-02-18

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