EA200701725A1 - Слои неявных кристаллов с низкой диэлектрической проницаемостью и наноструктуры для применения в высоких технологиях - Google Patents
Слои неявных кристаллов с низкой диэлектрической проницаемостью и наноструктуры для применения в высоких технологияхInfo
- Publication number
- EA200701725A1 EA200701725A1 EA200701725A EA200701725A EA200701725A1 EA 200701725 A1 EA200701725 A1 EA 200701725A1 EA 200701725 A EA200701725 A EA 200701725A EA 200701725 A EA200701725 A EA 200701725A EA 200701725 A1 EA200701725 A1 EA 200701725A1
- Authority
- EA
- Eurasian Patent Office
- Prior art keywords
- crystals
- implicit
- nanowires
- layers
- present
- Prior art date
Links
- 239000013078 crystal Substances 0.000 title abstract 8
- 239000002086 nanomaterial Substances 0.000 title abstract 2
- 238000005516 engineering process Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 abstract 5
- 239000002070 nanowire Substances 0.000 abstract 3
- 239000010410 layer Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 239000003989 dielectric material Substances 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
- 230000003287 optical effect Effects 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
- B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
Abstract
Настоящее изобретение предлагает способ получения пригодных для применения слоев неявных кристаллов с низким значением диэлектрической проницаемости на известных в технике полупроводниковых подложках, а также получения наноструктур, сформированных из этих неявных кристаллов, и относится к оптическим и электронным устройствам, которые могут быть получены из этих материалов. Полученные результаты показывают, что модифицирование структуры и химического состава матрицы монокристалла с использованием метода химического осаждения из паровой фазы обеспечивает получение высококачественных гомогенных слоев неявных кристаллов, которые образуют гладкую границу раздела с полупроводниковой подложкой. С помощью этого способа можно осуществить осаждение диэлектрических неявных кристаллов со скоростью 1 мкм/ч. Настоящее изобретение также обеспечивает способ получения микро- и нанопроволок путем преобразования неявных кристаллов в упорядоченные структуры. Настоящее изобретение также предлагает способ получения микро- и нанопроволок с размерами от нескольких нанометров до 1000 нм и длиной до 50 мкм. Неявные кристаллы, нанопроволоки и упорядоченные структуры могут быть использованы в будущих межкомпонентных соединениях в качестве межуровневых и интерметаллических диэлектриков, в производстве ячеек памяти со сверхвысокой плотностью, системах информационной безопасности в качестве кодовых генераторов, в производстве компонентов для фотоники и датчиков.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TR2005/00923A TR200500923A2 (tr) | 2005-03-16 | 2005-03-16 | İleri Teknoloji Uygulamaları için Küçük Dielektrik Sabitli K |
PCT/IB2006/050406 WO2006097858A2 (en) | 2005-03-16 | 2006-02-08 | Low-dielectric constant cryptocrystal layers and nanostructures |
Publications (2)
Publication Number | Publication Date |
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EA200701725A1 true EA200701725A1 (ru) | 2008-08-29 |
EA013649B1 EA013649B1 (ru) | 2010-06-30 |
Family
ID=36992107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EA200701725A EA013649B1 (ru) | 2005-03-16 | 2006-02-08 | Микрокристаллические и нанокристаллические структуры с низкой диэлектрической проницаемостью для применения в области высоких технологий |
Country Status (9)
Country | Link |
---|---|
US (1) | US20080191218A1 (ru) |
EP (1) | EP1878043B1 (ru) |
JP (1) | JP5112289B2 (ru) |
KR (1) | KR20070112410A (ru) |
CN (1) | CN101176189B (ru) |
CA (1) | CA2602365C (ru) |
EA (1) | EA013649B1 (ru) |
TR (1) | TR200500923A2 (ru) |
WO (1) | WO2006097858A2 (ru) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007197302A (ja) * | 2005-12-28 | 2007-08-09 | Sumitomo Electric Ind Ltd | Iii族窒化物結晶の製造方法および製造装置 |
WO2011123115A1 (en) * | 2010-03-31 | 2011-10-06 | Hewlett-Packard Development Company, L.P. | Nanoscale switching device |
CN102184873B (zh) * | 2011-04-21 | 2012-10-10 | 北京科技大学 | 一种快速制备金刚石-碳化硅电子封装材料的方法 |
US9337395B2 (en) | 2012-04-30 | 2016-05-10 | Tubitak | Methods for producing new silicon light source and devices |
DE102017109423A1 (de) * | 2017-05-03 | 2018-11-08 | Osram Gmbh | Verschlüsselung von Baken |
US11605760B2 (en) * | 2018-05-21 | 2023-03-14 | Intel Corporation | Micro light-emitting diode displays having nanophosphors |
US11605668B2 (en) * | 2018-05-21 | 2023-03-14 | Intel Corporation | Pixel architectures for low power micro light-emitting diode displays |
CN109813760A (zh) * | 2019-02-28 | 2019-05-28 | 江苏理工学院 | 一种氧化锌纳米线气体传感器及其制备方法 |
KR102581119B1 (ko) | 2020-06-16 | 2023-09-20 | 고려대학교 세종산학협력단 | 인화게르마늄 나노시트 및 이의 제조방법 |
KR102602180B1 (ko) | 2020-08-07 | 2023-11-13 | 고려대학교 세종산학협력단 | 비소화규소 나노시트 및 이의 제조방법 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1955821A (en) * | 1929-06-14 | 1934-04-24 | Ac Spark Plug Co | Ceramic process |
JPH0810672B2 (ja) * | 1987-07-03 | 1996-01-31 | 富士通株式会社 | 平板の接着方法 |
JP2766992B2 (ja) * | 1989-07-14 | 1998-06-18 | 富士通株式会社 | 半導体装置の製造方法 |
JPH06340416A (ja) * | 1990-08-29 | 1994-12-13 | Rhone Poulenc Chim | シリカ及び場合によっては四価元素の酸化物を基材とするゼオライトの製造法 |
JPH07283381A (ja) * | 1994-04-08 | 1995-10-27 | Canon Inc | 貼合わせ半導体基体の製造方法 |
US5470802A (en) * | 1994-05-20 | 1995-11-28 | Texas Instruments Incorporated | Method of making a semiconductor device using a low dielectric constant material |
JP3753805B2 (ja) * | 1996-09-19 | 2006-03-08 | 株式会社東芝 | 半導体試料の分解装置および試料分解方法 |
JPH10158010A (ja) * | 1996-11-26 | 1998-06-16 | Matsushita Electric Works Ltd | 酸化珪素被膜の製造方法 |
US6468927B1 (en) * | 2000-05-19 | 2002-10-22 | Applied Materials, Inc. | Method of depositing a nitrogen-doped FSG layer |
JP2002039927A (ja) * | 2000-07-19 | 2002-02-06 | Toshiba Ceramics Co Ltd | シリコンウェーハ表層の部分分析方法 |
JP2004123484A (ja) * | 2002-10-04 | 2004-04-22 | Crystal System:Kk | 金属酸化物膜およびその用途 |
JP4310415B2 (ja) * | 2003-04-28 | 2009-08-12 | 財団法人新産業創造研究機構 | 液相析出法によるマイクロパターニング方法 |
US7279369B2 (en) * | 2003-08-21 | 2007-10-09 | Intel Corporation | Germanium on insulator fabrication via epitaxial germanium bonding |
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2005
- 2005-03-16 TR TR2005/00923A patent/TR200500923A2/xx unknown
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2006
- 2006-02-08 EP EP06710851.4A patent/EP1878043B1/en active Active
- 2006-02-08 US US11/908,778 patent/US20080191218A1/en not_active Abandoned
- 2006-02-08 CA CA2602365A patent/CA2602365C/en active Active
- 2006-02-08 WO PCT/IB2006/050406 patent/WO2006097858A2/en active Application Filing
- 2006-02-08 EA EA200701725A patent/EA013649B1/ru unknown
- 2006-02-08 CN CN2006800170631A patent/CN101176189B/zh active Active
- 2006-02-08 JP JP2008501454A patent/JP5112289B2/ja active Active
- 2006-02-08 KR KR1020077023517A patent/KR20070112410A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
CA2602365C (en) | 2017-05-09 |
CN101176189B (zh) | 2011-05-11 |
EP1878043A2 (en) | 2008-01-16 |
EA013649B1 (ru) | 2010-06-30 |
JP5112289B2 (ja) | 2013-01-09 |
WO2006097858A3 (en) | 2007-07-19 |
CA2602365A1 (en) | 2006-09-21 |
TR200500923A2 (tr) | 2010-02-22 |
US20080191218A1 (en) | 2008-08-14 |
EP1878043B1 (en) | 2021-11-03 |
CN101176189A (zh) | 2008-05-07 |
JP2008537844A (ja) | 2008-09-25 |
WO2006097858A2 (en) | 2006-09-21 |
KR20070112410A (ko) | 2007-11-23 |
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