DK1461810T3 - En fremgangsmåde til læsning af en passiv matrix-adresserbar indretning og en indretning til udförelse af fremgangsmåden - Google Patents

En fremgangsmåde til læsning af en passiv matrix-adresserbar indretning og en indretning til udförelse af fremgangsmåden

Info

Publication number
DK1461810T3
DK1461810T3 DK02780189T DK02780189T DK1461810T3 DK 1461810 T3 DK1461810 T3 DK 1461810T3 DK 02780189 T DK02780189 T DK 02780189T DK 02780189 T DK02780189 T DK 02780189T DK 1461810 T3 DK1461810 T3 DK 1461810T3
Authority
DK
Denmark
Prior art keywords
cells
bit lines
passive matrix
word
reading
Prior art date
Application number
DK02780189T
Other languages
Danish (da)
English (en)
Inventor
Per Broems
Christer Karlsson
Original Assignee
Thin Film Electronics Asa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thin Film Electronics Asa filed Critical Thin Film Electronics Asa
Application granted granted Critical
Publication of DK1461810T3 publication Critical patent/DK1461810T3/da

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Inspection Of Paper Currency And Valuable Securities (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Image Analysis (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
DK02780189T 2001-11-30 2002-10-29 En fremgangsmåde til læsning af en passiv matrix-adresserbar indretning og en indretning til udförelse af fremgangsmåden DK1461810T3 (da)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NO20015879A NO314524B1 (no) 2001-11-30 2001-11-30 Fremgangsmåte til lesing av celler i en passiv matriseadresserbar innretning, samt innretning for utförelse av fremgangsmåten

Publications (1)

Publication Number Publication Date
DK1461810T3 true DK1461810T3 (da) 2006-12-11

Family

ID=19913096

Family Applications (1)

Application Number Title Priority Date Filing Date
DK02780189T DK1461810T3 (da) 2001-11-30 2002-10-29 En fremgangsmåde til læsning af en passiv matrix-adresserbar indretning og en indretning til udförelse af fremgangsmåden

Country Status (14)

Country Link
US (1) US6982895B2 (no)
EP (1) EP1461810B1 (no)
JP (4) JP2005518618A (no)
KR (1) KR100700812B1 (no)
CN (1) CN1701386B (no)
AT (1) ATE336067T1 (no)
AU (1) AU2002343260B8 (no)
CA (1) CA2467865A1 (no)
DE (1) DE60213869T2 (no)
DK (1) DK1461810T3 (no)
ES (1) ES2269777T3 (no)
NO (1) NO314524B1 (no)
RU (1) RU2275698C2 (no)
WO (1) WO2003046923A1 (no)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6756620B2 (en) * 2001-06-29 2004-06-29 Intel Corporation Low-voltage and interface damage-free polymer memory device
US6624457B2 (en) 2001-07-20 2003-09-23 Intel Corporation Stepped structure for a multi-rank, stacked polymer memory device and method of making same
NO315399B1 (no) * 2002-03-01 2003-08-25 Thin Film Electronics Asa Minnecelle
NO324607B1 (no) 2003-11-24 2007-11-26 Thin Film Electronics Asa Fremgangsmate for a betjene et datalagringsapparat som benytter passiv matriseadressering
JP4639049B2 (ja) * 2004-01-14 2011-02-23 パトレネラ キャピタル リミテッド， エルエルシー メモリ
NO324029B1 (no) 2004-09-23 2007-07-30 Thin Film Electronics Asa Lesemetode og deteksjonsanordning
KR100866751B1 (ko) * 2006-12-27 2008-11-03 주식회사 하이닉스반도체 강유전체 소자를 적용한 반도체 메모리 장치 및 그리프레쉬 방법
EP1944763A1 (en) * 2007-01-12 2008-07-16 STMicroelectronics S.r.l. Reading circuit and method for data storage system
US20080220557A1 (en) * 2007-03-06 2008-09-11 Atmel Corporation Sensor manufacture with data storage
KR100934159B1 (ko) * 2008-09-18 2009-12-31 한국과학기술원 강유전체 또는 일렉트렛 메모리 장치
EP3411950A1 (en) * 2016-02-04 2018-12-12 Fraunhofer Gesellschaft zur Förderung der angewandten Forschung E.V. Matrix power amplifier
US9886571B2 (en) 2016-02-16 2018-02-06 Xerox Corporation Security enhancement of customer replaceable unit monitor (CRUM)
US10978169B2 (en) 2017-03-17 2021-04-13 Xerox Corporation Pad detection through pattern analysis
US10497521B1 (en) 2018-10-29 2019-12-03 Xerox Corporation Roller electric contact
US11309034B2 (en) * 2020-07-15 2022-04-19 Ferroelectric Memory Gmbh Memory cell arrangement and methods thereof

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4169258A (en) * 1976-04-19 1979-09-25 Rockwell International Corporation One-third selection scheme for addressing a ferroelectric matrix arrangement
FR2621757A1 (fr) * 1987-10-09 1989-04-14 Thomson Csf Reseau neuronal programmable a polymere ferroelectrique
JPH0677434A (ja) * 1992-08-27 1994-03-18 Hitachi Ltd 半導体記憶装置
JPH0991970A (ja) * 1995-09-26 1997-04-04 Olympus Optical Co Ltd 非破壊型強誘電体メモリ及びその駆動方法
JP3327071B2 (ja) * 1995-10-16 2002-09-24 ソニー株式会社 強誘電体記憶装置
JPH09128960A (ja) * 1995-11-01 1997-05-16 Olympus Optical Co Ltd 強誘電体メモリ装置
JP2001229666A (ja) * 1999-12-07 2001-08-24 Seiko Epson Corp メモリ装置及びそのデータ読出し方法
JP3606367B2 (ja) * 1999-12-08 2005-01-05 セイコーエプソン株式会社 メモリデバイス及びその製造方法並びに電子機器
NO20004236L (no) * 2000-08-24 2002-02-25 Thin Film Electronics Asa Ikke-flyktig passiv matriseinnretning og fremgangsmåte for utlesing av samme
NO312699B1 (no) * 2000-07-07 2002-06-17 Thin Film Electronics Asa Adressering av minnematrise
US6466473B2 (en) * 2001-03-30 2002-10-15 Intel Corporation Method and apparatus for increasing signal to sneak ratio in polarizable cross-point matrix memory arrays
US6522568B1 (en) * 2001-07-24 2003-02-18 Intel Corporation Ferroelectric memory and method for reading the same

Also Published As

Publication number Publication date
NO20015879D0 (no) 2001-11-30
DE60213869T2 (de) 2006-12-07
CN1701386A (zh) 2005-11-23
NO20015879A (no) 2003-03-31
RU2275698C2 (ru) 2006-04-27
WO2003046923A1 (en) 2003-06-05
KR20040058315A (ko) 2004-07-03
JP2013033588A (ja) 2013-02-14
ATE336067T1 (de) 2006-09-15
JP2014146413A (ja) 2014-08-14
JP5743987B2 (ja) 2015-07-01
KR100700812B1 (ko) 2007-03-27
EP1461810A1 (en) 2004-09-29
CA2467865A1 (en) 2003-06-05
US20030103386A1 (en) 2003-06-05
US6982895B2 (en) 2006-01-03
ES2269777T3 (es) 2007-04-01
AU2002343260A1 (en) 2003-06-10
DE60213869D1 (de) 2006-09-21
EP1461810B1 (en) 2006-08-09
AU2002343260B8 (en) 2006-11-23
NO314524B1 (no) 2003-03-31
CN1701386B (zh) 2011-12-14
JP2009110654A (ja) 2009-05-21
AU2002343260B2 (en) 2006-10-12
JP2005518618A (ja) 2005-06-23
RU2004119046A (ru) 2006-01-10

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