DE69941652D1 - Verfahren zur Herstellung eines Silizium-auf-Isolator-Substrats - Google Patents

Verfahren zur Herstellung eines Silizium-auf-Isolator-Substrats

Info

Publication number
DE69941652D1
DE69941652D1 DE69941652T DE69941652T DE69941652D1 DE 69941652 D1 DE69941652 D1 DE 69941652D1 DE 69941652 T DE69941652 T DE 69941652T DE 69941652 T DE69941652 T DE 69941652T DE 69941652 D1 DE69941652 D1 DE 69941652D1
Authority
DE
Germany
Prior art keywords
silicon
producing
insulator substrate
insulator
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69941652T
Other languages
English (en)
Inventor
Kiyofumi Sakaguchi
Nobuhiko Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69941652D1 publication Critical patent/DE69941652D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
DE69941652T 1998-06-18 1999-06-16 Verfahren zur Herstellung eines Silizium-auf-Isolator-Substrats Expired - Lifetime DE69941652D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP17140298 1998-06-18
JP15644299A JP3762144B2 (ja) 1998-06-18 1999-06-03 Ｓｏｉ基板の作製方法

Publications (1)

Publication Number Publication Date
DE69941652D1 true DE69941652D1 (de) 2010-01-07

Family

ID=26484193

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69941652T Expired - Lifetime DE69941652D1 (de) 1998-06-18 1999-06-16 Verfahren zur Herstellung eines Silizium-auf-Isolator-Substrats

Country Status (7)

Country Link
US (1) US6313014B1 (de)
EP (1) EP0966034B1 (de)
JP (1) JP3762144B2 (de)
KR (1) KR100358638B1 (de)
CN (1) CN1155065C (de)
DE (1) DE69941652D1 (de)
TW (1) TW468278B (de)

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WO2001028000A1 (fr) * 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Procede de fabrication d'une tranche de soi, et tranche de soi
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US6461933B2 (en) * 2000-12-30 2002-10-08 Texas Instruments Incorporated SPIMOX/SIMOX combination with ITOX option
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JP2002289820A (ja) * 2001-03-28 2002-10-04 Nippon Steel Corp Ｓｉｍｏｘ基板の製造方法およびｓｉｍｏｘ基板
DE10131249A1 (de) * 2001-06-28 2002-05-23 Wacker Siltronic Halbleitermat Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material
US6555451B1 (en) * 2001-09-28 2003-04-29 The United States Of America As Represented By The Secretary Of The Navy Method for making shallow diffusion junctions in semiconductors using elemental doping
US20030134486A1 (en) * 2002-01-16 2003-07-17 Zhongze Wang Semiconductor-on-insulator comprising integrated circuitry
US6506654B1 (en) * 2002-03-26 2003-01-14 Advanced Micro Devices, Inc. Source-side stacking fault body-tie for partially-depleted SOI MOSFET hysteresis control
JP4376490B2 (ja) * 2002-07-19 2009-12-02 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2004119943A (ja) * 2002-09-30 2004-04-15 Renesas Technology Corp 半導体ウェハおよびその製造方法
US7192886B2 (en) * 2002-10-25 2007-03-20 Intersurface Dynamics, Inc. Method for using additives in the caustic etching of silicon for obtaining improved surface characteristics
TW200428637A (en) * 2003-01-23 2004-12-16 Shinetsu Handotai Kk SOI wafer and production method thereof
JP4442560B2 (ja) * 2003-02-19 2010-03-31 信越半導体株式会社 Ｓｏｉウエーハの製造方法
JP4854917B2 (ja) * 2003-03-18 2012-01-18 信越半導体株式会社 Ｓｏｉウェーハ及びその製造方法
FR2857895B1 (fr) * 2003-07-23 2007-01-26 Soitec Silicon On Insulator Procede de preparation de surface epiready sur films minces de sic
US6911376B2 (en) * 2003-10-01 2005-06-28 Wafermasters Selective heating using flash anneal
US7473656B2 (en) * 2003-10-23 2009-01-06 International Business Machines Corporation Method for fast and local anneal of anti-ferromagnetic (AF) exchange-biased magnetic stacks
KR20060114623A (ko) * 2003-10-24 2006-11-07 소니 가부시끼 가이샤 반도체 기판의 제조 방법 및 반도체 기판
JP2005210062A (ja) * 2003-12-26 2005-08-04 Canon Inc 半導体部材とその製造方法、及び半導体装置
US7887632B2 (en) 2004-01-15 2011-02-15 Japan Science And Technology Agency Process for producing monocrystal thin film and monocrystal thin film device
US7718009B2 (en) * 2004-08-30 2010-05-18 Applied Materials, Inc. Cleaning submicron structures on a semiconductor wafer surface
DE102005007599B3 (de) * 2005-02-18 2006-05-11 Infineon Technologies Austria Ag Verfahren zur Herstellung einer Feldstoppzone
US7244659B2 (en) * 2005-03-10 2007-07-17 Micron Technology, Inc. Integrated circuits and methods of forming a field effect transistor
US20060228492A1 (en) * 2005-04-07 2006-10-12 Sumco Corporation Method for manufacturing SIMOX wafer
CN101228613A (zh) * 2005-07-22 2008-07-23 胜高股份有限公司 Simox晶片的制造方法及用该方法制造的simox晶片
JP5157075B2 (ja) * 2006-03-27 2013-03-06 株式会社Ｓｕｍｃｏ Ｓｉｍｏｘウェーハの製造方法
JP2007266059A (ja) * 2006-03-27 2007-10-11 Sumco Corp Ｓｉｍｏｘウェーハの製造方法
JP2008004821A (ja) * 2006-06-23 2008-01-10 Sumco Corp 貼り合わせウェーハの製造方法
US7557002B2 (en) * 2006-08-18 2009-07-07 Micron Technology, Inc. Methods of forming transistor devices
US7989322B2 (en) * 2007-02-07 2011-08-02 Micron Technology, Inc. Methods of forming transistors
JP5700617B2 (ja) * 2008-07-08 2015-04-15 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US7927975B2 (en) * 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
JP2012104808A (ja) * 2010-10-14 2012-05-31 Dainippon Screen Mfg Co Ltd 熱処理装置および熱処理方法
CN102586886A (zh) * 2012-03-10 2012-07-18 天津市环欧半导体材料技术有限公司 一种用于去除硅晶片表面氧沉积物的硅晶片退火方法
US20140130854A1 (en) * 2012-11-12 2014-05-15 Samsung Sdi Co., Ltd. Photoelectric device and the manufacturing method thereof
KR102384962B1 (ko) 2015-11-27 2022-04-11 에스케이하이닉스 주식회사 반도체 메모리 장치
CN111470880A (zh) * 2019-01-23 2020-07-31 元创绿能科技股份有限公司 具有多孔隙的离子交换膜及其制造方法
JP7319059B2 (ja) * 2019-02-25 2023-08-01 エア・ウォーター株式会社 ペリクル中間体の製造方法およびペリクルの製造方法
CN110006727A (zh) * 2019-04-10 2019-07-12 深圳市锐骏半导体股份有限公司 一种离子注入机稳定性的监控方法
CN112490113A (zh) * 2020-11-12 2021-03-12 武汉新芯集成电路制造有限公司 一种半导体器件的制作方法
CN113421849B (zh) * 2021-06-09 2023-01-03 中环领先半导体材料有限公司 一种带绝缘埋层的硅衬底的制备工艺

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JPS62123098A (ja) 1985-11-22 1987-06-04 Toshiba Ceramics Co Ltd シリコン単結晶の製造方法
JPS6472533A (en) 1987-09-11 1989-03-17 Nippon Telegraph & Telephone Manufacture of single crystal semiconductor substrate
US5310689A (en) 1990-04-02 1994-05-10 Motorola, Inc. Method of forming a SIMOX structure
EP1251556B1 (de) * 1992-01-30 2010-03-24 Canon Kabushiki Kaisha Herstellungsverfahren für Halbleitersubstrat
US5429955A (en) 1992-10-26 1995-07-04 Texas Instruments Incorporated Method for constructing semiconductor-on-insulator
US5458755A (en) 1992-11-09 1995-10-17 Canon Kabushiki Kaisha Anodization apparatus with supporting device for substrate to be treated
JP3036619B2 (ja) 1994-03-23 2000-04-24 コマツ電子金属株式会社 Ｓｏｉ基板の製造方法およびｓｏｉ基板
JPH0837286A (ja) 1994-07-21 1996-02-06 Toshiba Microelectron Corp 半導体基板および半導体基板の製造方法
JPH0846161A (ja) 1994-07-29 1996-02-16 Mitsubishi Materials Corp Ｓｏｉ基板及びその製造方法
DE19623791A1 (de) 1996-06-14 1997-12-18 Linde Ag Verfahren zur Entfernung von Stickoxiden aus Gasen
US5989981A (en) 1996-07-05 1999-11-23 Nippon Telegraph And Telephone Corporation Method of manufacturing SOI substrate
JPH1041241A (ja) 1996-07-26 1998-02-13 Sharp Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
KR100358638B1 (ko) 2002-10-25
KR20000006300A (ko) 2000-01-25
JP3762144B2 (ja) 2006-04-05
CN1155065C (zh) 2004-06-23
EP0966034B1 (de) 2009-11-25
US6313014B1 (en) 2001-11-06
TW468278B (en) 2001-12-11
JP2000077352A (ja) 2000-03-14
CN1241016A (zh) 2000-01-12
EP0966034A1 (de) 1999-12-22

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