DE69940625D1 - Logikgatterzelle - Google Patents

Logikgatterzelle

Info

Publication number
DE69940625D1
DE69940625D1 DE69940625T DE69940625T DE69940625D1 DE 69940625 D1 DE69940625 D1 DE 69940625D1 DE 69940625 T DE69940625 T DE 69940625T DE 69940625 T DE69940625 T DE 69940625T DE 69940625 D1 DE69940625 D1 DE 69940625D1
Authority
DE
Germany
Prior art keywords
logic gate
inverting logic
diffusion regions
gate cell
step diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69940625T
Other languages
English (en)
Inventor
Kazuo Taki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
A I L Corp
Original Assignee
A I L Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by A I L Corp filed Critical A I L Corp
Application granted granted Critical
Publication of DE69940625D1 publication Critical patent/DE69940625D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Logic Circuits (AREA)
DE69940625T 1998-06-18 1999-06-16 Logikgatterzelle Expired - Lifetime DE69940625D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20851398 1998-06-18

Publications (1)

Publication Number Publication Date
DE69940625D1 true DE69940625D1 (de) 2009-05-07

Family

ID=16557419

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69940625T Expired - Lifetime DE69940625D1 (de) 1998-06-18 1999-06-16 Logikgatterzelle

Country Status (6)

Country Link
US (1) US6329845B1 (de)
EP (1) EP0966041B1 (de)
JP (1) JP3110422B2 (de)
AT (1) ATE426920T1 (de)
DE (1) DE69940625D1 (de)
TW (1) TW469628B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4334660B2 (ja) * 1999-04-05 2009-09-30 パナソニック株式会社 ラッチアップ検証方法及び検証装置
US6624656B1 (en) * 1999-10-15 2003-09-23 Triscend Corporation Input/output circuit with user programmable functions
JP4366914B2 (ja) * 2002-09-25 2009-11-18 日本電気株式会社 表示装置用駆動回路及びそれを用いた表示装置
JP4412893B2 (ja) * 2002-11-25 2010-02-10 シャープ株式会社 半導体集積回路およびその製造方法
KR20050099259A (ko) * 2004-04-09 2005-10-13 삼성전자주식회사 고속 플립플롭들 및 이를 이용한 복합 게이트들
JP4149980B2 (ja) * 2004-09-17 2008-09-17 シャープ株式会社 半導体製造装置の製造方法
US20070013425A1 (en) * 2005-06-30 2007-01-18 Burr James B Lower minimum retention voltage storage elements
JP2010129843A (ja) * 2008-11-28 2010-06-10 Renesas Electronics Corp 半導体集積回路におけるセルデータ生成方法、及び、半導体集積回路の設計方法
US20110018602A1 (en) * 2009-07-24 2011-01-27 Texas Instruments Incorporated Edge-sensitive feedback-controlled pulse generator
JP2013172155A (ja) * 2012-02-17 2013-09-02 Renesas Electronics Corp 半導体装置
TWI656622B (zh) * 2014-09-23 2019-04-11 聯華電子股份有限公司 積體電路佈局結構
US9577635B2 (en) * 2015-01-15 2017-02-21 Qualcomm Incorporated Clock-gating cell with low area, low power, and low setup time
KR102497218B1 (ko) * 2016-04-29 2023-02-07 삼성전자 주식회사 복합 논리 셀을 포함하는 집적 회로
US10402529B2 (en) 2016-11-18 2019-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and layout of an integrated circuit
US11055463B1 (en) * 2020-04-01 2021-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods for gate array with partial common inputs

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111347A (ja) 1981-12-24 1983-07-02 Matsushita Electric Ind Co Ltd 半導体装置
JPS62189739A (ja) * 1986-02-17 1987-08-19 Hitachi Ltd 半導体集積回路装置
JP2632420B2 (ja) * 1989-02-23 1997-07-23 三菱電機株式会社 半導体集積回路
JPH0382140A (ja) 1989-08-25 1991-04-08 Hitachi Ltd 半導体集積回路装置
JP3079599B2 (ja) * 1990-04-20 2000-08-21 セイコーエプソン株式会社 半導体集積回路及びその製造方法
US5764533A (en) * 1995-08-01 1998-06-09 Sun Microsystems, Inc. Apparatus and methods for generating cell layouts
US5903174A (en) * 1995-12-20 1999-05-11 Cypress Semiconductor Corp. Method and apparatus for reducing skew among input signals within an integrated circuit
JP3100568B2 (ja) 1997-09-09 2000-10-16 エイ・アイ・エル株式会社 小面積伝送ゲートセル

Also Published As

Publication number Publication date
JP3110422B2 (ja) 2000-11-20
US6329845B1 (en) 2001-12-11
EP0966041A2 (de) 1999-12-22
EP0966041B1 (de) 2009-03-25
JP2000077635A (ja) 2000-03-14
US20020000833A1 (en) 2002-01-03
TW469628B (en) 2001-12-21
EP0966041A3 (de) 2000-10-25
ATE426920T1 (de) 2009-04-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition