DE69835184D1 - DRAM-Zelle mit Graben-Kondensator und vertikalem Transistor - Google Patents

DRAM-Zelle mit Graben-Kondensator und vertikalem Transistor

Info

Publication number
DE69835184D1
DE69835184D1 DE69835184T DE69835184T DE69835184D1 DE 69835184 D1 DE69835184 D1 DE 69835184D1 DE 69835184 T DE69835184 T DE 69835184T DE 69835184 T DE69835184 T DE 69835184T DE 69835184 D1 DE69835184 D1 DE 69835184D1
Authority
DE
Germany
Prior art keywords
dram cell
vertical transistor
trench capacitor
trench
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69835184T
Other languages
English (en)
Other versions
DE69835184T2 (de
Inventor
Johann Alsmeier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE69835184D1 publication Critical patent/DE69835184D1/de
Application granted granted Critical
Publication of DE69835184T2 publication Critical patent/DE69835184T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
DE69835184T 1997-06-11 1998-05-28 DRAM-Zelle mit Graben-Kondensator und vertikalem Transistor Expired - Fee Related DE69835184T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US87278097A 1997-06-11 1997-06-11
US872780 1997-06-11

Publications (2)

Publication Number Publication Date
DE69835184D1 true DE69835184D1 (de) 2006-08-24
DE69835184T2 DE69835184T2 (de) 2007-06-14

Family

ID=25360277

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69835184T Expired - Fee Related DE69835184T2 (de) 1997-06-11 1998-05-28 DRAM-Zelle mit Graben-Kondensator und vertikalem Transistor

Country Status (6)

Country Link
EP (1) EP0884785B1 (de)
JP (1) JPH1117151A (de)
KR (1) KR100481035B1 (de)
CN (1) CN1202012A (de)
DE (1) DE69835184T2 (de)
TW (1) TW425718B (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080618A (en) * 1998-03-31 2000-06-27 Siemens Aktiengesellschaft Controllability of a buried device layer
US6197641B1 (en) * 1998-08-28 2001-03-06 Lucent Technologies Inc. Process for fabricating vertical transistors
US6255683B1 (en) * 1998-12-29 2001-07-03 Infineon Technologies Ag Dynamic random access memory
US6204140B1 (en) * 1999-03-24 2001-03-20 Infineon Technologies North America Corp. Dynamic random access memory
US6190971B1 (en) * 1999-05-13 2001-02-20 International Business Machines Corporation Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region
US6339239B1 (en) * 2000-06-23 2002-01-15 International Business Machines Corporation DRAM cell layout for node capacitance enhancement
US6551874B2 (en) * 2001-06-22 2003-04-22 Infineon Technologies, Ag Self-aligned STI process using nitride hard mask
US6617213B2 (en) * 2002-01-25 2003-09-09 Infineon Technologies Ag Method for achieving high self-aligning vertical gate studs relative to the support isolation level
DE10220584B3 (de) * 2002-05-08 2004-01-08 Infineon Technologies Ag Dynamische Speicherzelle und Verfahren zum Herstellen derselben
US6579759B1 (en) * 2002-08-23 2003-06-17 International Business Machines Corporation Formation of self-aligned buried strap connector
US7459743B2 (en) * 2005-08-24 2008-12-02 International Business Machines Corporation Dual port gain cell with side and top gated read transistor
US9837258B2 (en) 2015-05-22 2017-12-05 Honeywell International Inc. Ion trap with variable pitch electrodes
CN105609503A (zh) * 2016-01-25 2016-05-25 中国科学院微电子研究所 存储单元、存储器件及电子设备
US11217589B2 (en) * 2019-10-04 2022-01-04 Nanya Technology Corporation Semiconductor device and method of manufacturing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0760859B2 (ja) * 1985-11-19 1995-06-28 沖電気工業株式会社 半導体装置及びその製造方法
US5183774A (en) * 1987-11-17 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of making a semiconductor memory device
JPH07112049B2 (ja) * 1992-01-09 1995-11-29 インターナショナル・ビジネス・マシーンズ・コーポレイション ダイナミック・ランダム・アクセス・メモリ・デバイスおよび製造方法
US5360758A (en) * 1993-12-03 1994-11-01 International Business Machines Corporation Self-aligned buried strap for trench type DRAM cells
US5395786A (en) * 1994-06-30 1995-03-07 International Business Machines Corporation Method of making a DRAM cell with trench capacitor
US5614431A (en) * 1995-12-20 1997-03-25 International Business Machines Corporation Method of making buried strap trench cell yielding an extended transistor

Also Published As

Publication number Publication date
KR100481035B1 (ko) 2005-05-16
CN1202012A (zh) 1998-12-16
DE69835184T2 (de) 2007-06-14
EP0884785B1 (de) 2006-07-12
TW425718B (en) 2001-03-11
KR19990006511A (ko) 1999-01-25
EP0884785A2 (de) 1998-12-16
JPH1117151A (ja) 1999-01-22
EP0884785A3 (de) 2001-10-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee