DE69915704D1 - Ampic dram - Google Patents
Ampic dramInfo
- Publication number
- DE69915704D1 DE69915704D1 DE69915704T DE69915704T DE69915704D1 DE 69915704 D1 DE69915704 D1 DE 69915704D1 DE 69915704 T DE69915704 T DE 69915704T DE 69915704 T DE69915704 T DE 69915704T DE 69915704 D1 DE69915704 D1 DE 69915704D1
- Authority
- DE
- Germany
- Prior art keywords
- ampic dram
- ampic
- dram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Databases & Information Systems (AREA)
- Computer Hardware Design (AREA)
- Multimedia (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Dram (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/200,377 US6272567B1 (en) | 1998-11-24 | 1998-11-24 | System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed |
US200377 | 1998-11-24 | ||
PCT/IB1999/001782 WO2000031745A1 (en) | 1998-11-24 | 1999-11-08 | Ampic dram |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69915704D1 true DE69915704D1 (de) | 2004-04-22 |
DE69915704T2 DE69915704T2 (de) | 2005-03-31 |
Family
ID=22741461
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69915704T Expired - Lifetime DE69915704T2 (de) | 1998-11-24 | 1999-11-08 | Ampic dram |
Country Status (6)
Country | Link |
---|---|
US (1) | US6272567B1 (de) |
EP (1) | EP1177558B1 (de) |
AU (1) | AU6483299A (de) |
CA (1) | CA2351656A1 (de) |
DE (1) | DE69915704T2 (de) |
WO (1) | WO2000031745A1 (de) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6757791B1 (en) * | 1999-03-30 | 2004-06-29 | Cisco Technology, Inc. | Method and apparatus for reordering packet data units in storage queues for reading and writing memory |
US6477169B1 (en) * | 1999-05-14 | 2002-11-05 | Nortel Networks Limited | Multicast and unicast scheduling for a network device |
JP2003512746A (ja) * | 1999-05-21 | 2003-04-02 | エイヴィシー・システムズ | フリット・キャッシングを備えたファブリック・ルータ |
US6671792B1 (en) * | 2000-04-28 | 2003-12-30 | Hewlett-Packard Development Company, L.P. | Share masks and alias for directory coherency |
US7302704B1 (en) | 2000-06-16 | 2007-11-27 | Bbn Technologies Corp | Excising compromised routers from an ad-hoc network |
GB2374703A (en) * | 2001-04-19 | 2002-10-23 | Snell & Wilcox Ltd | Digital video store |
US6603683B2 (en) * | 2001-06-25 | 2003-08-05 | International Business Machines Corporation | Decoding scheme for a stacked bank architecture |
US7417986B1 (en) * | 2001-09-04 | 2008-08-26 | Cisco Technology, Inc. | Shared buffer switch interface |
US7269198B1 (en) | 2001-11-19 | 2007-09-11 | Bbn Technologies Corp. | Systems and methods for beaconing in wireless networks with low probability of detection |
US7421257B1 (en) | 2001-11-30 | 2008-09-02 | Stragent, Llc | Receiver scheduling in ad hoc wireless networks |
US7403521B2 (en) * | 2001-12-03 | 2008-07-22 | Intel Corporation | Multicast and broadcast operations in ethernet switches |
US7609693B2 (en) * | 2002-06-04 | 2009-10-27 | Alcatel-Lucent Usa Inc. | Multicast packet queuing |
US6907453B2 (en) * | 2002-09-18 | 2005-06-14 | Broadcom Corporation | Per CoS memory partitioning |
US7403536B2 (en) * | 2002-12-19 | 2008-07-22 | International Business Machines Corporation | Method and system for resequencing data packets switched through a parallel packet switch |
US20040131055A1 (en) * | 2003-01-06 | 2004-07-08 | Juan-Carlos Calderon | Memory management free pointer pool |
US7983239B1 (en) | 2003-01-07 | 2011-07-19 | Raytheon Bbn Technologies Corp. | Systems and methods for constructing a virtual model of a multi-hop, multi-access network |
US20040246902A1 (en) * | 2003-06-02 | 2004-12-09 | Weinstein Joseph J. | Systems and methods for synchronizing multple copies of a database using datablase digest |
US7881229B2 (en) | 2003-08-08 | 2011-02-01 | Raytheon Bbn Technologies Corp. | Systems and methods for forming an adjacency graph for exchanging network routing data |
US7606927B2 (en) | 2003-08-27 | 2009-10-20 | Bbn Technologies Corp | Systems and methods for forwarding data units in a communications network |
US8166204B2 (en) * | 2003-08-29 | 2012-04-24 | Raytheon Bbn Technologies Corp. | Systems and methods for automatically placing nodes in an ad hoc network |
US7174437B2 (en) * | 2003-10-16 | 2007-02-06 | Silicon Graphics, Inc. | Memory access management in a shared memory multi-processor system |
US7668083B1 (en) | 2003-10-28 | 2010-02-23 | Bbn Technologies Corp. | Systems and methods for forwarding data in a communications network |
US7369512B1 (en) | 2003-11-06 | 2008-05-06 | Bbn Technologies Corp. | Systems and methods for efficient packet distribution in an ad hoc network |
US7539190B2 (en) * | 2004-01-05 | 2009-05-26 | Topside Research, Llc | Multicasting in a shared address space |
US7532623B2 (en) * | 2004-03-24 | 2009-05-12 | Bbn Technologies Corp. | Methods for wireless mesh multicasting |
US7574555B2 (en) * | 2005-03-18 | 2009-08-11 | Emc Corporation | Memory system having daisy chained memory controllers |
JP4761078B2 (ja) * | 2005-08-29 | 2011-08-31 | 日本電気株式会社 | マルチキャストノード装置とマルチキャスト転送方法ならびにプログラム |
US7773621B2 (en) * | 2006-09-16 | 2010-08-10 | Mips Technologies, Inc. | Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch |
US7990989B2 (en) * | 2006-09-16 | 2011-08-02 | Mips Technologies, Inc. | Transaction selector employing transaction queue group priorities in multi-port switch |
US7961745B2 (en) * | 2006-09-16 | 2011-06-14 | Mips Technologies, Inc. | Bifurcated transaction selector supporting dynamic priorities in multi-port switch |
US7760748B2 (en) * | 2006-09-16 | 2010-07-20 | Mips Technologies, Inc. | Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch |
US8736627B2 (en) * | 2006-12-19 | 2014-05-27 | Via Technologies, Inc. | Systems and methods for providing a shared buffer in a multiple FIFO environment |
US8239566B2 (en) * | 2008-02-28 | 2012-08-07 | Silicon Graphics International, Corp. | Non-saturating fairness protocol and method for NACKing systems |
US8139504B2 (en) * | 2009-04-07 | 2012-03-20 | Raytheon Bbn Technologies Corp. | System, device, and method for unifying differently-routed networks using virtual topology representations |
US8566491B2 (en) | 2011-01-31 | 2013-10-22 | Qualcomm Incorporated | System and method for improving throughput of data transfers using a shared non-deterministic bus |
KR20120119960A (ko) * | 2011-04-21 | 2012-11-01 | 삼성전자주식회사 | 마이크로 범프 연결성을 테스트할 수 있는 반도체 장치 |
US20130205051A1 (en) * | 2012-02-07 | 2013-08-08 | Qualcomm Incorporated | Methods and Devices for Buffer Allocation |
US20140376549A1 (en) * | 2013-06-20 | 2014-12-25 | Mediatek Inc. | Packet processing apparatus and method for processing input packet according to packet processing list created based on forwarding decision made for input packet |
US10120809B2 (en) * | 2015-09-26 | 2018-11-06 | Intel Corporation | Method, apparatus, and system for allocating cache using traffic class |
US10331601B2 (en) * | 2016-04-15 | 2019-06-25 | Infinera Corporation | Systems, apparatus, and methods for efficient space to time conversion of OTU multiplexed signal |
US20180239532A1 (en) * | 2017-02-23 | 2018-08-23 | Western Digital Technologies, Inc. | Techniques for performing a non-blocking control sync operation |
CN113032295B (zh) * | 2021-02-25 | 2022-08-16 | 西安电子科技大学 | 一种数据包二级缓存方法、系统及应用 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01280860A (ja) * | 1988-05-06 | 1989-11-13 | Hitachi Ltd | マルチポートキヤツシユメモリを有するマルチプロセツサシステム |
US5442747A (en) * | 1993-09-27 | 1995-08-15 | Auravision Corporation | Flexible multiport multiformat burst buffer |
US5799209A (en) * | 1995-12-29 | 1998-08-25 | Chatter; Mukesh | Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration |
US5918074A (en) * | 1997-07-25 | 1999-06-29 | Neonet Llc | System architecture for and method of dual path data processing and management of packets and/or cells and the like |
US6108758A (en) * | 1997-08-29 | 2000-08-22 | Intel Corporation | Multiple masters in a memory control system |
US6067595A (en) * | 1997-09-23 | 2000-05-23 | Icore Technologies, Inc. | Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories |
KR100261218B1 (ko) * | 1997-12-08 | 2000-07-01 | 윤종용 | 반도체 메모리 장치의 핀 어사인먼트 방법 및 패킷 단위의 신호를 입력으로 하는 반도체 메모리장치 |
US6085290A (en) * | 1998-03-10 | 2000-07-04 | Nexabit Networks, Llc | Method of and apparatus for validating data read out of a multi port internally cached dynamic random access memory (AMPIC DRAM) |
US6138219A (en) * | 1998-03-27 | 2000-10-24 | Nexabit Networks Llc | Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access |
US6003121A (en) * | 1998-05-18 | 1999-12-14 | Intel Corporation | Single and multiple channel memory detection and sizing |
US6112267A (en) * | 1998-05-28 | 2000-08-29 | Digital Equipment Corporation | Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels |
US6122680A (en) * | 1998-06-18 | 2000-09-19 | Lsi Logic Corporation | Multiple channel data communication buffer with separate single port transmit and receive memories having a unique channel for each communication port and with fixed arbitration |
-
1998
- 1998-11-24 US US09/200,377 patent/US6272567B1/en not_active Expired - Lifetime
-
1999
- 1999-11-08 DE DE69915704T patent/DE69915704T2/de not_active Expired - Lifetime
- 1999-11-08 CA CA002351656A patent/CA2351656A1/en not_active Abandoned
- 1999-11-08 AU AU64832/99A patent/AU6483299A/en not_active Abandoned
- 1999-11-08 WO PCT/IB1999/001782 patent/WO2000031745A1/en active IP Right Grant
- 1999-11-08 EP EP99952738A patent/EP1177558B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO2000031745A1 (en) | 2000-06-02 |
DE69915704T2 (de) | 2005-03-31 |
CA2351656A1 (en) | 2000-06-02 |
AU6483299A (en) | 2000-06-13 |
EP1177558B1 (de) | 2004-03-17 |
US6272567B1 (en) | 2001-08-07 |
EP1177558A1 (de) | 2002-02-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de | ||
8370 | Indication related to discontinuation of the patent is to be deleted | ||
8364 | No opposition during term of opposition |