GB2374703A

GB2374703A - Digital video store

Info

Publication number: GB2374703A
Application number: GB0109663A
Authority: GB
Inventors: David Oades; Howard Teece
Original assignee: Snell and Wilcox Ltd
Current assignee: Snell Advanced Media Ltd
Priority date: 2001-04-19
Filing date: 2001-04-19
Publication date: 2002-10-23
Also published as: WO2002086902A1; GB0109663D0

Abstract

In a digital video store, there is provided an input and output terminal arrangement, a plurality of addressable memory modules 209 and a read/write arrangement for reading and writing video data between the terminal means and appropriate locations within the plurality of memory modules. The read/write arrangement comprises a common data path communicating with the terminal arrangement and linking the memory modules in series. Typically, the common data path comprises a data bus along which passes all data written to and read from the store, and a set of latches the respective settings of which select the memory modules to be written to or read from.

Description

DATA STORAGE AND MANIPULATION This invention concerns data storage and manipulation, and in a particular example, the storage and manipulation of high-definition video data.

Memory subassemblies have been developed for use in personal computers and at the time of filing are typically capable of storing 128 million 72-bit words with data clock speeds up to 200 MHz. These are suitable for the digital storage of highdefinition television but the practical implementation of storage devices for large volumes of such data is difficult. In particular, if very high input and output data rates are to be achieved, the input and output connections to the memory modules must be designed as short transmission lines.

It is therefore an object of certain aspects of the present invention to address these problems, and to provide a fast data storage system with good power efficiency and low complexity.

Accordingly, the present invention consists in one aspect in a digital video store comprising an input and output terminal arrangement; a plurality of addressable memory modules and a read/write arrangement for reading and writing video data between the terminal means and appropriate locations within the plurality of memory modules ; characterised in that the read/write arrangement comprises a common data path communicating with the terminal arrangement and linking the memory modules in series.

Preferably, the common data path comprises a data bus a ! ong which passes all data written to and read from the store and a set of latches the respective settings of which select the memory modules to be written to or read from.

Advantageously, the store further comprises a video signal processor communicating with the common data path and adapted to process video data being written to or read from the memory modules.

Suitably, the store further comprises a packetizer serving to packetize data received at the terminal arrangement.

In one form of the invention, the store is adapted to store audio or other data in addition to video data, the packetizer being adapted to identify within a packet header, the video or other nature of data contained within each packet.

The invention will now be described by way of example with reference to the drawings in which: Figure 1 shows a prior art HD video store; Figure 2 shows a storage device according to an embodiment of the invention; and Figure 3 shows an alternative embodiment of part of Figure 2.

Figure 1 shows a prior art"RAM recorder"in which an input digital HDTV signal sequence is written into an array of memory modules and, possibly simultaneously, an output digital HDTV signal sequence is read from the memory and output. The input data (101) is fed to a multiplexer (102) which has individual outputs for each one of an array of memory sub-assemblies (104). A memory controller (105) routes consecutive data words to consecutive addresses in the memory array by suitable control of the addresses fed to the memory modules and routing of the multiplexer (102). If the length of the sequence is too great for all the data to be read into one memory module, the multiplexer (102) switches the data to another module at the appropriate point.

The reading and output of data from the memory is carried according to the reverse of the above process. The memory controller (105) causes the de-multiplexer (106) to route the data from the appropriate memory module to the output (107) and controls the read addresses so as to output the consecutive words of the required video sequence.

It is important to note that any increase in the number of memory modules requires increased complexity of the multiplexer and de-multiplexer and corresponding increased numbers of individual data input and output connections to and from the memory modules.

Referring now to Figure 2 an improved data recorder in accordance with an embodiment of the invention will be described. The device has inputs for digital HDTV (201), metadata (202) and digital audio (203). Each of these inputs is fed to an associated"packetiser" (204) (205) (206) which reformats the streaming input data

into discrete data packets, each of which incorporates"header"data indicating its source, type and relative temporal position in the relevant data stream.

The packets are input synchronously to a packet router (207) which outputs the packets serially onto a single, high speed data bus (208). This data bus feeds a pipeline sequence of memory modules (209) in which the output of the first module is latched and fed to the input of the next module. The data output of the last module in the pipeline feeds a packet router (210) which sorts the packets according to their data type and outputs them to the relevant one of the output modules (211), (212) and (213).

These output modules reformat the asynchronous, packetised data from the relevant router output as synchronous, streaming data for output.

A control system (214) monitors the operation of the input and output routers (207) (210) and controls the addressing and mode of operation of the memory modules. Memory modules which are not involved in reading or writing data pass the data along the bus without processing (other than delay).

An alternative arrangement for the memory modules is shown in Figure (3).

Here the pipeline consists of a sequence of data latches with a memory module connected in parallel with each latch input. In this configuration modules which are not in use can be set to a high impedance condition, modules can read data from the bus, and modules can output data to the bus when the associated previous latch output is set to a high impedance condition.

It will be appreciated that the memory can be made very large without increasing the complexity of the data path; the increased memory size results in greater control complexity and greater data latency. The latter problem can be overcome by increasing the speed of the bus; in practice a bus clock-rate of the order of 130 MHz can be used which enables HDTV sequences to be streamed into and out of the memory concurrently with associated audio and data. The novel structure fully exploits the high speed of the memory and is particularly suitable for streaming data. This flexibility is particularly useful in the field of video effects where, for example, a video sequence can be replayed from the memory together with a sequence of filter coefficients and memory addresses (as metadata) which will be used in a digital video effects machine (DVE) to produce novel manipulations and combinations of recorded and live video.

It should be understood that this invention has been described by way of examples only and that numerous modifications are possible without departing from the scope of the invention.

Claims

1. A digital video store comprising an input and output terminal arrangement; a plurality of addressable memory modules and a read/write arrangement for reading and writing video data between the terminal means and appropriate locations within the plurality of memory modules; characterised in that the read/write arrangement comprises a common data path communicating with the terminal arrangement and linking the memory modules in series.

2. A digital video store according to Claim 1, wherein the common riota path comprises a data bus along which passes all data written to and read from the store and a set of latches the respective settings of which select the memory modules to be written to or read from.

3. A digital video store according to Claim 1 or Claim 2, further comprising a video signal processor communicating with the common data path and adapted to process video data being written to or read from the memory modules.

4. A digital video store according to any one of the preceding claims, further comprising a packetizer serving to packetize data received at the terminal arrangement.

5. A digital video store according to Claim 4, adapted to store audio or other data in addition to video data, the packetizer being adapted to identify within a packet header, the video or other nature of data contained within each packet.