DE69828547D1 - Verbesserte Abgleichschaltungen für dynamischen Zugriffspeicher und Verfahren dafür - Google Patents

Verbesserte Abgleichschaltungen für dynamischen Zugriffspeicher und Verfahren dafür

Info

Publication number
DE69828547D1
DE69828547D1 DE69828547T DE69828547T DE69828547D1 DE 69828547 D1 DE69828547 D1 DE 69828547D1 DE 69828547 T DE69828547 T DE 69828547T DE 69828547 T DE69828547 T DE 69828547T DE 69828547 D1 DE69828547 D1 DE 69828547D1
Authority
DE
Germany
Prior art keywords
access memory
methods therefor
dynamic access
tuning circuits
improved dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69828547T
Other languages
English (en)
Other versions
DE69828547T2 (de
Inventor
Heinz Hoenigschmid
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE69828547D1 publication Critical patent/DE69828547D1/de
Application granted granted Critical
Publication of DE69828547T2 publication Critical patent/DE69828547T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4094Bit-line management or control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
DE69828547T 1997-06-30 1998-06-05 Verbesserte Abgleichschaltungen für dynamischen Zugriffspeicher und Verfahren dafür Expired - Fee Related DE69828547T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US884855 1997-06-30
US08/884,855 US5875138A (en) 1997-06-30 1997-06-30 Dynamic access memory equalizer circuits and methods therefor

Publications (2)

Publication Number Publication Date
DE69828547D1 true DE69828547D1 (de) 2005-02-17
DE69828547T2 DE69828547T2 (de) 2005-12-22

Family

ID=25385568

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69828547T Expired - Fee Related DE69828547T2 (de) 1997-06-30 1998-06-05 Verbesserte Abgleichschaltungen für dynamischen Zugriffspeicher und Verfahren dafür

Country Status (6)

Country Link
US (1) US5875138A (de)
EP (1) EP0889480B1 (de)
JP (1) JP4376983B2 (de)
KR (1) KR100522902B1 (de)
DE (1) DE69828547T2 (de)
TW (1) TW385443B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19822750A1 (de) * 1998-05-20 1999-11-25 Siemens Ag Halbleiterspeicher mit differentiellen Bitleitungen
KR100439037B1 (ko) * 2002-08-06 2004-07-03 삼성전자주식회사 반도체 메모리 장치의 비트 라인 프리차지 회로
KR101185757B1 (ko) * 2005-06-20 2012-09-25 고에키자이단호진 고쿠사이카가쿠 신고우자이단 층간 절연막 및 배선 구조와 그것들의 제조 방법
JP4392694B2 (ja) * 2007-01-10 2010-01-06 エルピーダメモリ株式会社 半導体記憶装置
KR101015123B1 (ko) 2007-07-26 2011-02-16 주식회사 하이닉스반도체 셀 어레이 블럭 내에 이퀄라이즈 트랜지스터가 형성되는반도체 메모리 장치
KR102070623B1 (ko) 2013-07-09 2020-01-29 삼성전자 주식회사 비트 라인 등화 회로

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4651183A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation High density one device memory cell arrays
JP2590171B2 (ja) * 1988-01-08 1997-03-12 株式会社日立製作所 半導体記憶装置
JPH0729373A (ja) * 1993-07-08 1995-01-31 Mitsubishi Electric Corp 半導体記憶装置
KR0152168B1 (ko) * 1994-04-15 1998-10-01 모리시다 요이치 반도체 기억장치

Also Published As

Publication number Publication date
DE69828547T2 (de) 2005-12-22
JP4376983B2 (ja) 2009-12-02
US5875138A (en) 1999-02-23
KR100522902B1 (ko) 2006-04-21
EP0889480B1 (de) 2005-01-12
EP0889480A3 (de) 1999-08-04
TW385443B (en) 2000-03-21
KR19990007263A (ko) 1999-01-25
JPH1187642A (ja) 1999-03-30
EP0889480A2 (de) 1999-01-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee