DE69823101D1 - Energieverteilungssystem für Halbleiterchip - Google Patents

Energieverteilungssystem für Halbleiterchip

Info

Publication number
DE69823101D1
DE69823101D1 DE69823101T DE69823101T DE69823101D1 DE 69823101 D1 DE69823101 D1 DE 69823101D1 DE 69823101 T DE69823101 T DE 69823101T DE 69823101 T DE69823101 T DE 69823101T DE 69823101 D1 DE69823101 D1 DE 69823101D1
Authority
DE
Germany
Prior art keywords
power distribution
distribution system
semiconductor chips
chips
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69823101T
Other languages
English (en)
Other versions
DE69823101T2 (de
Inventor
Toan D Nguyen
Michael T Johnson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Application granted granted Critical
Publication of DE69823101D1 publication Critical patent/DE69823101D1/de
Publication of DE69823101T2 publication Critical patent/DE69823101T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Wire Bonding (AREA)
DE69823101T 1997-06-25 1998-06-24 Energieverteilungssystem für Halbleiterchip Expired - Fee Related DE69823101T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US882714 1992-05-14
US08/882,714 US6025616A (en) 1997-06-25 1997-06-25 Power distribution system for semiconductor die

Publications (2)

Publication Number Publication Date
DE69823101D1 true DE69823101D1 (de) 2004-05-19
DE69823101T2 DE69823101T2 (de) 2004-11-11

Family

ID=25381185

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69823101T Expired - Fee Related DE69823101T2 (de) 1997-06-25 1998-06-24 Energieverteilungssystem für Halbleiterchip

Country Status (3)

Country Link
US (1) US6025616A (de)
EP (1) EP0887800B1 (de)
DE (1) DE69823101T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2771853B1 (fr) * 1997-11-28 2000-02-11 Sgs Thomson Microelectronics Plot de test de circuit integre
JP4330676B2 (ja) * 1998-08-17 2009-09-16 株式会社東芝 半導体集積回路
US6538337B2 (en) * 2000-08-17 2003-03-25 Samsung Electronics Co., Ltd. Ball grid array package for providing constant internal voltage via a PCB substrate routing configuration
US6306745B1 (en) 2000-09-21 2001-10-23 Taiwan Semiconductor Manufacturing Company Chip-area-efficient pattern and method of hierarchal power routing
US6763511B2 (en) * 2001-07-02 2004-07-13 Nec Electronics Corporation Semiconductor integrated circuit having macro cells and designing method of the same
US20030037271A1 (en) * 2001-08-15 2003-02-20 Dean Liu Reducing clock skew by power supply isolation
US6584596B2 (en) 2001-09-24 2003-06-24 International Business Machines Corporation Method of designing a voltage partitioned solder-bump package
US6770982B1 (en) 2002-01-16 2004-08-03 Marvell International, Ltd. Semiconductor device power distribution system and method
US8258616B1 (en) 2002-01-16 2012-09-04 Marvell International Ltd. Semiconductor dice having a shielded area created under bond wires connecting pairs of bonding pads
US6861762B1 (en) * 2002-05-01 2005-03-01 Marvell Semiconductor Israel Ltd. Flip chip with novel power and ground arrangement
US6858945B2 (en) * 2002-08-21 2005-02-22 Broadcom Corporation Multi-concentric pad arrangements for integrated circuit pads
JP4141322B2 (ja) * 2003-06-13 2008-08-27 Ｎｅｃエレクトロニクス株式会社 半導体集積回路の自動配線方法及び半導体集積回路の設計のプログラム
JP4904670B2 (ja) * 2004-06-02 2012-03-28 富士通セミコンダクター株式会社 半導体装置
US20070029661A1 (en) * 2005-08-04 2007-02-08 Texas Instruments Incorporated Power plane design and jumper wire bond for voltage drop minimization
US9196598B1 (en) * 2014-06-12 2015-11-24 Freescale Semiconductor, Inc. Semiconductor device having power distribution using bond wires
US10217717B2 (en) 2015-11-18 2019-02-26 Stmicroelectronics (Rousset) Sas Distribution of electronic circuit power supply potentials

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5878439A (ja) * 1981-11-04 1983-05-12 Nec Corp 半導体集積回路装置
JPS6114734A (ja) * 1984-06-29 1986-01-22 Fujitsu Ltd 半導体集積回路装置及びその製造方法
JPS62188261A (ja) * 1986-01-16 1987-08-17 Sony Corp メモリ装置
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
JPH0286131A (ja) * 1988-09-22 1990-03-27 Seiko Epson Corp 半導体集積装置
JPH02278849A (ja) * 1989-04-20 1990-11-15 Fujitsu Ltd 半導体装置の製造方法
JPH0329342A (ja) * 1989-06-26 1991-02-07 Toshiba Corp 半導体装置
US5231305A (en) * 1990-03-19 1993-07-27 Texas Instruments Incorporated Ceramic bonding bridge
JPH0410624A (ja) * 1990-04-27 1992-01-14 Hitachi Ltd 半導体集積回路
JP3074003B2 (ja) * 1990-08-21 2000-08-07 株式会社日立製作所 半導体集積回路装置
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5391920A (en) * 1991-07-09 1995-02-21 Yamaha Corporation Semiconductor device having peripheral metal wiring
US5229639A (en) * 1991-10-31 1993-07-20 International Business Machines Corporation Low powder distribution inductance lead frame for semiconductor chips
EP0645810A4 (de) * 1993-04-06 1997-04-16 Tokuyama Corp Packung für halbleiterchip.
US5384487A (en) * 1993-05-05 1995-01-24 Lsi Logic Corporation Off-axis power branches for interior bond pad arrangements
US5641988A (en) * 1993-12-22 1997-06-24 Vlsi Technology, Inc. Multi-layered, integrated circuit package having reduced parasitic noise characteristics
JP2594762B2 (ja) * 1994-08-16 1997-03-26 九州日本電気株式会社 フラットパッケージ
US5668389A (en) * 1994-12-02 1997-09-16 Intel Corporation Optimized power bus structure
JP2674553B2 (ja) * 1995-03-30 1997-11-12 日本電気株式会社 半導体装置
US5672911A (en) * 1996-05-30 1997-09-30 Lsi Logic Corporation Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package
US5744870A (en) * 1996-06-07 1998-04-28 Micron Technology, Inc. Memory device with multiple input/output connections
US5789791A (en) * 1996-08-27 1998-08-04 National Semiconductor Corporation Multi-finger MOS transistor with reduced gate resistance
US5789807A (en) * 1996-10-15 1998-08-04 International Business Machines Corporation On-chip power distribution for improved decoupling
US5831315A (en) * 1997-02-05 1998-11-03 Alliance Semiconductor Corporation Highly integrated low voltage SRAM array with low resistance Vss lines

Also Published As

Publication number Publication date
DE69823101T2 (de) 2004-11-11
EP0887800A2 (de) 1998-12-30
US6025616A (en) 2000-02-15
EP0887800A3 (de) 1999-07-14
EP0887800B1 (de) 2004-04-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee