FR2771853B1 - Plot de test de circuit integre - Google Patents

Plot de test de circuit integre

Info

Publication number
FR2771853B1
FR2771853B1 FR9715328A FR9715328A FR2771853B1 FR 2771853 B1 FR2771853 B1 FR 2771853B1 FR 9715328 A FR9715328 A FR 9715328A FR 9715328 A FR9715328 A FR 9715328A FR 2771853 B1 FR2771853 B1 FR 2771853B1
Authority
FR
France
Prior art keywords
integrated circuit
circuit test
test plot
plot
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9715328A
Other languages
English (en)
Other versions
FR2771853A1 (fr
Inventor
Michel Vallet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Priority to FR9715328A priority Critical patent/FR2771853B1/fr
Priority to US09/193,443 priority patent/US6246072B1/en
Publication of FR2771853A1 publication Critical patent/FR2771853A1/fr
Application granted granted Critical
Publication of FR2771853B1 publication Critical patent/FR2771853B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/305—Contactless testing using electron beams
    • G01R31/307—Contactless testing using electron beams of integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
FR9715328A 1997-11-28 1997-11-28 Plot de test de circuit integre Expired - Fee Related FR2771853B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9715328A FR2771853B1 (fr) 1997-11-28 1997-11-28 Plot de test de circuit integre
US09/193,443 US6246072B1 (en) 1997-11-28 1998-11-17 Integrated circuit test pad

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9715328A FR2771853B1 (fr) 1997-11-28 1997-11-28 Plot de test de circuit integre

Publications (2)

Publication Number Publication Date
FR2771853A1 FR2771853A1 (fr) 1999-06-04
FR2771853B1 true FR2771853B1 (fr) 2000-02-11

Family

ID=9514177

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9715328A Expired - Fee Related FR2771853B1 (fr) 1997-11-28 1997-11-28 Plot de test de circuit integre

Country Status (2)

Country Link
US (1) US6246072B1 (fr)
FR (1) FR2771853B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2854731B1 (fr) * 2003-05-05 2005-08-12 St Microelectronics Sa Circuit integre et procede de test associe
FR2879295B1 (fr) * 2004-12-14 2007-03-16 St Microelectronics Sa Structure de test pour circuit electronique integre
US7749885B2 (en) * 2006-12-15 2010-07-06 Micron Technology, Inc. Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5775438A (en) * 1980-10-29 1982-05-12 Toshiba Corp Semiconductor element
JPS61252641A (ja) * 1985-05-02 1986-11-10 Matsushita Electronics Corp 半導体集積回路の検査方法
CA1271849A (fr) * 1986-02-27 1990-07-17 Schlumberger Technologies, Inc. Test de plaquettes de semiconducteur par faisceau electronique
US4901136A (en) * 1987-07-14 1990-02-13 General Electric Company Multi-chip interconnection package
JPH065691B2 (ja) 1987-09-26 1994-01-19 株式会社東芝 半導体素子の試験方法および試験装置
JPH02268439A (ja) * 1989-04-10 1990-11-02 Hitachi Ltd 半導体集積回路装置
EP0473144A3 (en) * 1990-08-28 1992-04-15 Nec Corporation Semiconductor integrated circuit comprising interconnections
JP3432963B2 (ja) * 1995-06-15 2003-08-04 沖電気工業株式会社 半導体集積回路
US5877551A (en) * 1996-11-18 1999-03-02 Olin Corporation Semiconductor package having a ground or power ring and a metal substrate
US5818102A (en) * 1995-12-29 1998-10-06 Lsi Logic Corporation System having integrated circuit package with lead frame having internal power and ground busses
US5773895A (en) * 1996-04-03 1998-06-30 Intel Corporation Anchor provisions to prevent mold delamination in an overmolded plastic array package
US6025616A (en) * 1997-06-25 2000-02-15 Honeywell Inc. Power distribution system for semiconductor die
US5895967A (en) * 1997-07-07 1999-04-20 Texas Instruments Incorporated Ball grid array package having a deformable metal layer and method
US5990547A (en) * 1998-03-02 1999-11-23 Motorola, Inc. Semiconductor device having plated contacts and method thereof
US5903050A (en) * 1998-04-30 1999-05-11 Lsi Logic Corporation Semiconductor package having capacitive extension spokes and method for making the same

Also Published As

Publication number Publication date
US6246072B1 (en) 2001-06-12
FR2771853A1 (fr) 1999-06-04

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Legal Events

Date Code Title Description
CD Change of name or company name
ST Notification of lapse

Effective date: 20070731