DE69800219T2 - Verfahren zur Herstellung einer Mehrlagenleiterplatte - Google Patents

Verfahren zur Herstellung einer Mehrlagenleiterplatte

Info

Publication number
DE69800219T2
DE69800219T2 DE69800219T DE69800219T DE69800219T2 DE 69800219 T2 DE69800219 T2 DE 69800219T2 DE 69800219 T DE69800219 T DE 69800219T DE 69800219 T DE69800219 T DE 69800219T DE 69800219 T2 DE69800219 T2 DE 69800219T2
Authority
DE
Germany
Prior art keywords
production
circuit board
printed circuit
multilayer printed
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69800219T
Other languages
English (en)
Other versions
DE69800219D1 (de
Inventor
Masashi Tachibana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69800219D1 publication Critical patent/DE69800219D1/de
Publication of DE69800219T2 publication Critical patent/DE69800219T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1056—Perforating lamina
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
DE69800219T 1997-04-04 1998-04-01 Verfahren zur Herstellung einer Mehrlagenleiterplatte Expired - Lifetime DE69800219T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP08638797A JP3324437B2 (ja) 1997-04-04 1997-04-04 多層プリント配線板の製造方法

Publications (2)

Publication Number Publication Date
DE69800219D1 DE69800219D1 (de) 2000-08-24
DE69800219T2 true DE69800219T2 (de) 2000-11-30

Family

ID=13885474

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69800219T Expired - Lifetime DE69800219T2 (de) 1997-04-04 1998-04-01 Verfahren zur Herstellung einer Mehrlagenleiterplatte

Country Status (4)

Country Link
US (1) US6270607B1 (de)
EP (1) EP0869705B1 (de)
JP (1) JP3324437B2 (de)
DE (1) DE69800219T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001045478A1 (fr) * 1999-12-14 2001-06-21 Matsushita Electric Industrial Co. Ltd. Carte a circuit imprime multicouche et procede de production
US6596406B2 (en) * 2000-12-28 2003-07-22 Nitto Denko Corporation Wiring board prepreg and manufacturing method thereof
US6815709B2 (en) * 2001-05-23 2004-11-09 International Business Machines Corporation Structure having flush circuitry features and method of making
JP2003031952A (ja) * 2001-07-12 2003-01-31 Meiko:Kk コア基板、それを用いた多層回路基板
JP2003078249A (ja) * 2001-09-06 2003-03-14 Fujitsu Ten Ltd 多層基板構造
EP1470744A2 (de) 2001-10-10 2004-10-27 Molex Incorporated Steckkartenverbinder und leiterplattenlayout
US6860000B2 (en) * 2002-02-15 2005-03-01 E.I. Du Pont De Nemours And Company Method to embed thick film components
JP2004119863A (ja) * 2002-09-27 2004-04-15 Sanyo Electric Co Ltd 回路装置およびその製造方法
JP4052295B2 (ja) 2004-08-25 2008-02-27 セイコーエプソン株式会社 多層配線基板の製造方法、電子デバイス及び電子機器
JP4608297B2 (ja) * 2004-12-06 2011-01-12 インターナショナル・ビジネス・マシーンズ・コーポレーション 積層配線基板の製造方法
JP2007134396A (ja) * 2005-11-08 2007-05-31 Fujifilm Corp プリント配線板用積層体、それを用いた多層金属配線パターン形成方法及び金属薄膜
US8933556B2 (en) * 2010-01-22 2015-01-13 Ibiden Co., Ltd. Wiring board
TWI558277B (zh) * 2014-08-19 2016-11-11 乾坤科技股份有限公司 電路板層間導電結構、磁性元件及其製作方法
DE102019108870A1 (de) * 2019-04-04 2020-10-08 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Träger mit verkleinerter Durchkontaktierung

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4383363A (en) * 1977-09-01 1983-05-17 Sharp Kabushiki Kaisha Method of making a through-hole connector
JPS6318697A (ja) 1986-07-11 1988-01-26 日本電気株式会社 多層配線基板
US5716663A (en) * 1990-02-09 1998-02-10 Toranaga Technologies Multilayer printed circuit
US5473120A (en) 1992-04-27 1995-12-05 Tokuyama Corporation Multilayer board and fabrication method thereof
JPH06223623A (ja) * 1992-12-28 1994-08-12 Internatl Business Mach Corp <Ibm> 銅を素材とするペーストおよびセラミックパッケージ
US5314742A (en) * 1993-03-31 1994-05-24 E. I. Du Pont De Nemours And Company Resin impregnated laminate for wiring board applications
US5652042A (en) * 1993-10-29 1997-07-29 Matsushita Electric Industrial Co., Ltd. Conductive paste compound for via hole filling, printed circuit board which uses the conductive paste
JP3290041B2 (ja) * 1995-02-17 2002-06-10 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層プリント基板、多層プリント基板の製造方法
US5699613A (en) * 1995-09-25 1997-12-23 International Business Machines Corporation Fine dimension stacked vias for a multiple layer circuit board structure

Also Published As

Publication number Publication date
JP3324437B2 (ja) 2002-09-17
US6270607B1 (en) 2001-08-07
EP0869705A1 (de) 1998-10-07
DE69800219D1 (de) 2000-08-24
EP0869705B1 (de) 2000-07-19
JPH10284841A (ja) 1998-10-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP