DE69733193D1 - Halbleiteranordnung mit einem Leitersubstrat - Google Patents

Halbleiteranordnung mit einem Leitersubstrat

Info

Publication number
DE69733193D1
DE69733193D1 DE69733193T DE69733193T DE69733193D1 DE 69733193 D1 DE69733193 D1 DE 69733193D1 DE 69733193 T DE69733193 T DE 69733193T DE 69733193 T DE69733193 T DE 69733193T DE 69733193 D1 DE69733193 D1 DE 69733193D1
Authority
DE
Germany
Prior art keywords
conductor substrate
semiconductor arrangement
semiconductor
arrangement
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69733193T
Other languages
English (en)
Other versions
DE69733193T2 (de
Inventor
Makoto Terui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69733193D1 publication Critical patent/DE69733193D1/de
Application granted granted Critical
Publication of DE69733193T2 publication Critical patent/DE69733193T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
DE69733193T 1997-02-12 1997-12-19 Halbleiteranordnung mit einem Leitersubstrat Expired - Fee Related DE69733193T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2742597 1997-02-12
JP02742597A JP3483720B2 (ja) 1997-02-12 1997-02-12 半導体装置

Publications (2)

Publication Number Publication Date
DE69733193D1 true DE69733193D1 (de) 2005-06-09
DE69733193T2 DE69733193T2 (de) 2006-03-02

Family

ID=12220764

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69733193T Expired - Fee Related DE69733193T2 (de) 1997-02-12 1997-12-19 Halbleiteranordnung mit einem Leitersubstrat

Country Status (6)

Country Link
US (1) US6060774A (de)
EP (1) EP0863549B1 (de)
JP (1) JP3483720B2 (de)
KR (1) KR100369879B1 (de)
CN (1) CN1124649C (de)
DE (1) DE69733193T2 (de)

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US6773965B2 (en) 1999-05-25 2004-08-10 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
US6268650B1 (en) * 1999-05-25 2001-07-31 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
US6372539B1 (en) 2000-03-20 2002-04-16 National Semiconductor Corporation Leadless packaging process using a conductive substrate
US6452255B1 (en) * 2000-03-20 2002-09-17 National Semiconductor, Corp. Low inductance leadless package
US6686652B1 (en) 2000-03-20 2004-02-03 National Semiconductor Locking lead tips and die attach pad for a leadless package apparatus and method
US6399415B1 (en) 2000-03-20 2002-06-04 National Semiconductor Corporation Electrical isolation in panels of leadless IC packages
US6534852B1 (en) * 2000-04-11 2003-03-18 Advanced Semiconductor Engineering, Inc. Ball grid array semiconductor package with improved strength and electric performance and method for making the same
US6750536B2 (en) * 2001-12-14 2004-06-15 Intel Corporation Current supply and support system for a thin package
JP2003229517A (ja) 2002-01-31 2003-08-15 Fujitsu Hitachi Plasma Display Ltd 半導体チップ実装基板及びフラットディスプレイ
SG114561A1 (en) * 2002-08-02 2005-09-28 Micron Technology Inc Integrated circuit and method of fabricating an integrated circuit that includes a frame carrier interposer
KR100499003B1 (ko) * 2002-12-12 2005-07-01 삼성전기주식회사 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법
JP4027820B2 (ja) * 2003-03-06 2007-12-26 シャープ株式会社 半導体装置及びその製造方法
JP4096831B2 (ja) * 2003-07-09 2008-06-04 日産自動車株式会社 半導体装置の実装構造
US7145249B2 (en) * 2004-03-29 2006-12-05 Intel Corporation Semiconducting device with folded interposer
US7378725B2 (en) * 2004-03-31 2008-05-27 Intel Corporation Semiconducting device with stacked dice
US20050285254A1 (en) * 2004-06-23 2005-12-29 Buot Joan R V Semiconducting device having stacked dice
JP4503039B2 (ja) * 2006-04-27 2010-07-14 三洋電機株式会社 回路装置
US20080073778A1 (en) * 2006-09-27 2008-03-27 Texas Instruments Incorporated Two-way heat extraction from packaged semiconductor chips
TWI315095B (en) * 2006-10-12 2009-09-21 Advanced Semiconductor Eng Semiconductor packaging structure having electromagnetic shielding function and method for manufacturing the same
JP4450031B2 (ja) 2007-08-22 2010-04-14 株式会社デンソー 半導体部品
MY165522A (en) * 2011-01-06 2018-04-02 Carsem M Sdn Bhd Leadframe packagewith die mounted on pedetal that isolates leads
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CN1124649C (zh) 2003-10-15
US6060774A (en) 2000-05-09
EP0863549A3 (de) 1999-02-24
DE69733193T2 (de) 2006-03-02
JPH10223672A (ja) 1998-08-21
KR19980069914A (ko) 1998-10-26
EP0863549B1 (de) 2005-05-04
CN1211073A (zh) 1999-03-17
EP0863549A2 (de) 1998-09-09
KR100369879B1 (ko) 2003-06-18
JP3483720B2 (ja) 2004-01-06

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