DE69732765T2 - Nullstromschaltung zur Verwendung während einer Verbindungsoption - Google Patents

Nullstromschaltung zur Verwendung während einer Verbindungsoption Download PDF

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Publication number
DE69732765T2
DE69732765T2 DE69732765T DE69732765T DE69732765T2 DE 69732765 T2 DE69732765 T2 DE 69732765T2 DE 69732765 T DE69732765 T DE 69732765T DE 69732765 T DE69732765 T DE 69732765T DE 69732765 T2 DE69732765 T2 DE 69732765T2
Authority
DE
Germany
Prior art keywords
signal
circuit
transistor
line
contacting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69732765T
Other languages
German (de)
English (en)
Other versions
DE69732765D1 (de
Inventor
Jiu An
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69732765D1 publication Critical patent/DE69732765D1/de
Publication of DE69732765T2 publication Critical patent/DE69732765T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69732765T 1997-06-16 1997-12-08 Nullstromschaltung zur Verwendung während einer Verbindungsoption Expired - Lifetime DE69732765T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US876213 1997-06-16
US08/876,213 US5920227A (en) 1997-06-16 1997-06-16 Zero current draw circuit for use during a bonding option

Publications (2)

Publication Number Publication Date
DE69732765D1 DE69732765D1 (de) 2005-04-21
DE69732765T2 true DE69732765T2 (de) 2005-08-11

Family

ID=25367212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69732765T Expired - Lifetime DE69732765T2 (de) 1997-06-16 1997-12-08 Nullstromschaltung zur Verwendung während einer Verbindungsoption

Country Status (4)

Country Link
US (1) US5920227A (https=)
EP (1) EP0886380B1 (https=)
JP (1) JPH1117119A (https=)
DE (1) DE69732765T2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW417267B (en) * 1997-11-20 2001-01-01 Davicom Semiconductor Inc Structure of bonding option
JP2000223576A (ja) * 1999-02-02 2000-08-11 Rohm Co Ltd 集積回路
JP3423904B2 (ja) * 1999-10-06 2003-07-07 沖電気工業株式会社 半導体集積回路
EP1132963B1 (en) 2000-03-08 2007-10-17 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
KR100426989B1 (ko) * 2001-06-13 2004-04-13 삼성전자주식회사 패키지 전원핀을 이용한 제어신호 인가방법 및 그에 따른집적회로 패키지 구조
US7131033B1 (en) 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
JP2006245063A (ja) 2005-02-28 2006-09-14 Nec Electronics Corp 半導体チップおよび半導体チップを搭載する半導体装置
EP2139114A1 (en) * 2008-06-23 2009-12-30 Dialog Semiconductor GmbH Ultra-low current push-buttom switch interface circuit
WO2016117072A1 (ja) * 2015-01-22 2016-07-28 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56153832A (en) * 1980-04-30 1981-11-28 Nec Corp Digital to analog converter
JPH03104315A (ja) * 1989-09-19 1991-05-01 Matsushita Electron Corp Ｃｍｏｓ半導体装置の入力端子電位固定回路
JPH0562465A (ja) * 1991-08-30 1993-03-12 Hitachi Ltd ボンデイングオプシヨン回路、及び半導体集積回路
DE69326284T2 (de) * 1992-06-10 2000-03-23 Nec Corp., Tokio/Tokyo Halbleiteranordnung mit anschlusswählender Schaltung
JPH06195476A (ja) * 1992-07-21 1994-07-15 Advanced Micro Devicds Inc マイクロコントローラを組入れる集積回路およびそれによる電力消費を減じるための方法
FR2694851B1 (fr) * 1992-08-12 1994-12-23 Sgs Thomson Microelectronics Circuit de tirage vers un état déterminé d'une entrée de circuit intégré.
EP0670548A1 (en) * 1994-02-28 1995-09-06 STMicroelectronics, Inc. Method and structure for recovering smaller density memories from larger density memories
US5684411A (en) * 1995-10-13 1997-11-04 Seiko Communications Systems, Inc. Self-configuring bus

Also Published As

Publication number Publication date
EP0886380A3 (en) 2000-02-16
JPH1117119A (ja) 1999-01-22
US5920227A (en) 1999-07-06
EP0886380A2 (en) 1998-12-23
DE69732765D1 (de) 2005-04-21
EP0886380B1 (en) 2005-03-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,