DE69729913D1 - Ätzverfahren zum Herstellen von Metallfilmstrukturen mit abgeschrägten Seitenwänden - Google Patents

Ätzverfahren zum Herstellen von Metallfilmstrukturen mit abgeschrägten Seitenwänden

Info

Publication number
DE69729913D1
DE69729913D1 DE69729913T DE69729913T DE69729913D1 DE 69729913 D1 DE69729913 D1 DE 69729913D1 DE 69729913 T DE69729913 T DE 69729913T DE 69729913 T DE69729913 T DE 69729913T DE 69729913 D1 DE69729913 D1 DE 69729913D1
Authority
DE
Germany
Prior art keywords
production
side walls
metal film
etching process
film structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69729913T
Other languages
English (en)
Other versions
DE69729913T2 (de
Inventor
Cheng-Yih Lin
Paul Patrick Mulgrew
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of DE69729913D1 publication Critical patent/DE69729913D1/de
Application granted granted Critical
Publication of DE69729913T2 publication Critical patent/DE69729913T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Inorganic Chemistry (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69729913T 1996-06-07 1997-05-27 Ätzverfahren zum Herstellen von Metallfilmstrukturen mit abgeschrägten Seitenwänden Expired - Lifetime DE69729913T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/664,227 US5670062A (en) 1996-06-07 1996-06-07 Method for producing tapered lines
US664227 1996-06-07

Publications (2)

Publication Number Publication Date
DE69729913D1 true DE69729913D1 (de) 2004-08-26
DE69729913T2 DE69729913T2 (de) 2005-08-25

Family

ID=24665132

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69729913T Expired - Lifetime DE69729913T2 (de) 1996-06-07 1997-05-27 Ätzverfahren zum Herstellen von Metallfilmstrukturen mit abgeschrägten Seitenwänden

Country Status (5)

Country Link
US (1) US5670062A (de)
EP (1) EP0812012B1 (de)
JP (1) JP3550272B2 (de)
KR (1) KR100455640B1 (de)
DE (1) DE69729913T2 (de)

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US5779929A (en) * 1996-10-07 1998-07-14 Lucent Technologies Inc. Thin film metallization for barium nanotitanate substrates
US6445004B1 (en) 1998-02-26 2002-09-03 Samsung Electronics Co., Ltd. Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
US6337520B1 (en) 1997-02-26 2002-01-08 Samsung Electronics Co., Ltd. Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and manufacturing method thereof
GB2338105B (en) * 1997-03-04 2000-04-12 Lg Electronics Inc Method of making a thin film transistor
KR100392909B1 (ko) 1997-08-26 2004-03-22 엘지.필립스 엘시디 주식회사 박막트랜지스터및그의제조방법
KR100248123B1 (ko) 1997-03-04 2000-03-15 구본준 박막트랜지스터및그의제조방법
JP2985124B2 (ja) * 1997-06-12 1999-11-29 株式会社日立製作所 液晶表示装置
KR100495807B1 (ko) * 1998-05-15 2005-10-12 삼성전자주식회사 배선용조성물,이조성물을이용한금속배선및그제조방법,이배선을이용한표시장치및그제조방법
KR20000003756A (ko) * 1998-06-29 2000-01-25 김영환 박막 트랜지스터 및 그의 제조방법
KR100356452B1 (ko) 1998-10-02 2002-10-18 가부시키가이샤 히타치세이사쿠쇼 액정 표시 장치 및 그 제조 방법
US6365917B1 (en) * 1998-11-25 2002-04-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2001044166A (ja) 1999-07-29 2001-02-16 Nec Akita Ltd 導電膜パターンの形成方法
DE19943521C2 (de) * 1999-09-09 2001-11-29 Dresden Ev Inst Festkoerper Verfahren zum Einstellen definierter Flankenwinkel beim Herstellen von Schichtstrukturen
TW480576B (en) 2000-05-12 2002-03-21 Semiconductor Energy Lab Semiconductor device and method for manufacturing same
SG116443A1 (en) * 2001-03-27 2005-11-28 Semiconductor Energy Lab Wiring and method of manufacturing the same, and wiring board and method of manufacturing the same.
US20060157709A1 (en) * 2002-08-20 2006-07-20 Koninklijke Philips Electronics N.V. Thin film transistor
KR100543001B1 (ko) 2003-09-03 2006-01-20 삼성에스디아이 주식회사 박막 트랜지스터 및 액티브 매트릭스 평판 표시 장치
US20050133479A1 (en) * 2003-12-19 2005-06-23 Youngner Dan W. Equipment and process for creating a custom sloped etch in a substrate
JP4085094B2 (ja) 2004-02-19 2008-04-30 シャープ株式会社 導電素子基板の製造方法、液晶表示装置の製造方法
KR101171175B1 (ko) 2004-11-03 2012-08-06 삼성전자주식회사 도전체용 식각액 및 이를 이용한 박막 트랜지스터표시판의 제조 방법
US20070155180A1 (en) * 2006-01-05 2007-07-05 Chunghwa Picture Tubes, Ltd. Thin film etching method
CN102575360B (zh) * 2009-10-02 2014-01-08 三菱瓦斯化学株式会社 用于抑制金属微细结构体的图案倒塌的处理液和使用其的金属微细结构体的制造方法
KR20120075037A (ko) * 2010-12-28 2012-07-06 삼성전자주식회사 반도체 소자의 제조 방법
US10147782B2 (en) 2016-07-18 2018-12-04 International Business Machines Corporation Tapered metal nitride structure
US10991582B2 (en) * 2016-12-21 2021-04-27 Canon Kabushiki Kaisha Template for imprint lithography including a recession, an apparatus of using the template, and a method of fabricating an article
DE102019120765B4 (de) 2018-09-27 2024-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zum bilden eines halbleiterbauelements
US11195754B2 (en) 2018-10-09 2021-12-07 International Business Machines Corporation Transistor with reduced gate resistance and improved process margin of forming self-aligned contact
KR102666776B1 (ko) * 2019-05-10 2024-05-21 삼성디스플레이 주식회사 박막 트랜지스터의 제조 방법, 표시 장치의 제조 방법 및 박막 트랜지스터 기판
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Also Published As

Publication number Publication date
KR100455640B1 (ko) 2005-01-17
JP3550272B2 (ja) 2004-08-04
US5670062A (en) 1997-09-23
KR980005705A (ko) 1998-03-30
EP0812012A1 (de) 1997-12-10
JPH1081981A (ja) 1998-03-31
EP0812012B1 (de) 2004-07-21
DE69729913T2 (de) 2005-08-25

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