DE69729242D1 - Halbleiterbauelement mit einer Isolationsdoppelwanne und deren Herstellungsmethode - Google Patents

Halbleiterbauelement mit einer Isolationsdoppelwanne und deren Herstellungsmethode

Info

Publication number
DE69729242D1
DE69729242D1 DE69729242T DE69729242T DE69729242D1 DE 69729242 D1 DE69729242 D1 DE 69729242D1 DE 69729242 T DE69729242 T DE 69729242T DE 69729242 T DE69729242 T DE 69729242T DE 69729242 D1 DE69729242 D1 DE 69729242D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor component
insulation double
double trough
trough
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69729242T
Other languages
English (en)
Other versions
DE69729242T2 (de
Inventor
Yutaka Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69729242D1 publication Critical patent/DE69729242D1/de
Application granted granted Critical
Publication of DE69729242T2 publication Critical patent/DE69729242T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/60—Peripheral circuit regions
    • H10B20/65—Peripheral circuit regions of memory structures of the ROM only type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Non-Volatile Memory (AREA)
DE69729242T 1996-06-14 1997-06-11 Halbleiterbauelement mit einer Isolationsdoppelwanne und deren Herstellungsmethode Expired - Fee Related DE69729242T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8175507A JPH104182A (ja) 1996-06-14 1996-06-14 半導体装置およびその製造方法
JP17550796 1996-06-14

Publications (2)

Publication Number Publication Date
DE69729242D1 true DE69729242D1 (de) 2004-07-01
DE69729242T2 DE69729242T2 (de) 2005-07-07

Family

ID=15997263

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69729242T Expired - Fee Related DE69729242T2 (de) 1996-06-14 1997-06-11 Halbleiterbauelement mit einer Isolationsdoppelwanne und deren Herstellungsmethode

Country Status (7)

Country Link
US (2) US6124623A (de)
EP (1) EP0813249B1 (de)
JP (1) JPH104182A (de)
KR (1) KR980006292A (de)
CN (1) CN1171630A (de)
DE (1) DE69729242T2 (de)
TW (1) TW476154B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465606B1 (ko) * 1998-06-30 2005-04-06 주식회사 하이닉스반도체 반도체소자의 삼중웰 제조방법
US6661044B2 (en) * 2001-10-22 2003-12-09 Winbond Electronics Corp. Method of manufacturing MOSEFT and structure thereof
KR20160011136A (ko) 2015-03-25 2016-01-29 한국기계연구원 내식성이 향상된 마그네슘 합금 및 이를 이용하여 제조한 마그네슘 합금 부재의 제조방법

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091324A (en) * 1990-08-10 1992-02-25 Advanced Micro Devices, Inc. Process for producing optimum intrinsic, long channel, and short channel mos devices in vlsi structures
DE69125794T2 (de) * 1990-11-23 1997-11-27 Texas Instruments Inc Verfahren zum gleichzeitigen Herstellen eines Feldeffekttransistors mit isoliertem Gate und eines Bipolartransistors
EP0543656B1 (de) 1991-11-20 1998-09-16 Fujitsu Limited Löschbare Halbleiterspeicheranordnung mit verbesserter Zuverlässigkeit
JPH05198666A (ja) * 1991-11-20 1993-08-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
IT1250233B (it) * 1991-11-29 1995-04-03 St Microelectronics Srl Procedimento per la fabbricazione di circuiti integrati in tecnologia mos.
KR950009815B1 (ko) * 1991-12-23 1995-08-28 삼성전자주식회사 트리플웰 구조를 가지는 고집적 반도체 메모리 장치
US5411908A (en) * 1992-05-28 1995-05-02 Texas Instruments Incorporated Flash EEPROM array with P-tank insulated from substrate by deep N-tank
KR960012303B1 (ko) * 1992-08-18 1996-09-18 삼성전자 주식회사 불휘발성 반도체메모리장치 및 그 제조방법
JP3002371B2 (ja) 1993-11-22 2000-01-24 富士通株式会社 半導体装置とその製造方法
JPH07176701A (ja) 1993-12-17 1995-07-14 Nec Corp 半導体装置とその製造方法
KR0138312B1 (ko) * 1994-05-13 1998-04-28 김광호 비휘발성 반도체 메모리장치의 제조방법
US5627099A (en) 1994-12-07 1997-05-06 Lsi Logic Japan Semiconductor, Inc. Method of manufacturing semiconductor device
US5494851A (en) 1995-01-18 1996-02-27 Micron Technology, Inc. Semiconductor processing method of providing dopant impurity into a semiconductor substrate
JP2679683B2 (ja) 1995-04-28 1997-11-19 日本電気株式会社 半導体装置の製造方法
US5604150A (en) * 1995-10-25 1997-02-18 Texas Instruments Incorporated Channel-stop process for use with thick-field isolation regions in triple-well structures
JP3008854B2 (ja) * 1996-07-12 2000-02-14 日本電気株式会社 不揮発性半導体記憶装置の製造方法

Also Published As

Publication number Publication date
US6124623A (en) 2000-09-26
TW476154B (en) 2002-02-11
EP0813249B1 (de) 2004-05-26
JPH104182A (ja) 1998-01-06
US6180455B1 (en) 2001-01-30
DE69729242T2 (de) 2005-07-07
KR980006292A (ko) 1998-03-30
CN1171630A (zh) 1998-01-28
EP0813249A1 (de) 1997-12-17

Similar Documents

Publication Publication Date Title
DE69935095D1 (de) Halbleiterbauelement und deren Herstellungsverfahren
DE69831903D1 (de) Halbleiterbauelement mit Kondensator und deren Herstellungsmethode
DE69534636D1 (de) Halbleitervorrichtung und deren Herstellungsverfahren
DE69739354D1 (de) Halbleiteranordnung und deren Herstellungsverfahren
DE69738012D1 (de) Halbleitervorrichtung und deren Herstellungsverfahren
KR950034612A (ko) 반도체 구조물 및 그 제조 방법
DE19544980B4 (de) Lichtemittierendes Bauelement mit einem isolierenden Substrat und Herstellverfahren für dieses Bauelement
DE69215176D1 (de) Solarzelle und deren Herstellungsmethode
EP0717450A3 (de) Vertikale Halbleiteranordnung mit isoliertem Gate und Vefahren zur Herstellung
KR950034858A (ko) 광기전력 소자, 그의 전극 구조 및 그의 제조방법
DE69818185D1 (de) Halbleiterverpackung und deren Herstellungsmethode
DE69904145D1 (de) Isolationsanordnung mit flansch und dessen herstellungsmethode
EP0771029A3 (de) Halbleitereinrichtung mit verbesserter Struktur zur Vermeidung von Rissen und Herstellungsverfahren
DE69528335D1 (de) Leiterrahmen mit Stufen, Halbleiterbaulelement und Herstellungsmethode
DE69617169D1 (de) Antisicherungsstruktur mit reduziertem leckstrom und herstellungsverfahren
DE69721411D1 (de) Halbleiteranordnung und Herstellungsverfahren dafür
DE69707845D1 (de) Wendelantenne mit integrierter breitbandspeisung und verfahren zu deren herstellung
DE69511726D1 (de) Halbleiteranordnung mit isoliertem gate
KR910007146A (ko) T형의 반도체 돌출부를 가지는 mosfet와 그 제조방법
DE69706910D1 (de) Herstellungsverfahren einer T-förmigen Gate-Elektrode in einem Halbleiterbauelement, und die T-förmige Gate-Elektrode
KR960012496A (ko) 반도체기억장치 및 그 제조방법
DE69724754D1 (de) Ladungsverringernde Schicht, Bilderzeugungsgerät und Herstellungsverfahren
GB2316227B (en) Insulated gate semiconductor device and method of manufacturing the same
KR960012313A (ko) 반도체 장치 및 그 제조방법
GB2336469B (en) Semiconductor device and manufacturing method of the same

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee