DE69727410D1 - Verfahren zum Entgräten von Leiterrahmen - Google Patents

Verfahren zum Entgräten von Leiterrahmen

Info

Publication number
DE69727410D1
DE69727410D1 DE69727410T DE69727410T DE69727410D1 DE 69727410 D1 DE69727410 D1 DE 69727410D1 DE 69727410 T DE69727410 T DE 69727410T DE 69727410 T DE69727410 T DE 69727410T DE 69727410 D1 DE69727410 D1 DE 69727410D1
Authority
DE
Germany
Prior art keywords
lead frames
deburring
deburring lead
frames
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69727410T
Other languages
English (en)
Other versions
DE69727410T2 (de
Inventor
Seiji Ichikawa
Junich Tanaka
Tomoaki Hiroakwa
Taku Sato
Tomoaki Kimura
Satoshi Murata
Tsutomu Kubota
Takeo Ogihara
Kenji Uchida
Kenji Watanabe
Tsutomu Noguti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Compound Semiconductor Devices Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Compound Semiconductor Devices Ltd filed Critical NEC Compound Semiconductor Devices Ltd
Application granted granted Critical
Publication of DE69727410D1 publication Critical patent/DE69727410D1/de
Publication of DE69727410T2 publication Critical patent/DE69727410T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4835—Cleaning, e.g. removing of solder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Processing And Handling Of Plastics And Other Materials For Molding In General (AREA)
DE69727410T 1996-03-05 1997-03-04 Entgraten Expired - Lifetime DE69727410T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8047196A JP2760339B2 (ja) 1996-03-05 1996-03-05 リードフレームのばり取り方法およびリードフレーム用ばり取り装置
JP4719696 1996-03-05

Publications (2)

Publication Number Publication Date
DE69727410D1 true DE69727410D1 (de) 2004-03-11
DE69727410T2 DE69727410T2 (de) 2004-12-02

Family

ID=12768382

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69727410T Expired - Lifetime DE69727410T2 (de) 1996-03-05 1997-03-04 Entgraten

Country Status (8)

Country Link
US (1) US5956574A (de)
EP (1) EP0794559B1 (de)
JP (1) JP2760339B2 (de)
KR (1) KR100216164B1 (de)
AU (1) AU709916B2 (de)
CA (1) CA2199112C (de)
DE (1) DE69727410T2 (de)
TW (1) TW343367B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3462806B2 (ja) * 1999-08-06 2003-11-05 三洋電機株式会社 半導体装置およびその製造方法
US6353257B1 (en) * 2000-05-19 2002-03-05 Siliconware Precision Industries Co., Ltd. Semiconductor package configuration based on lead frame having recessed and shouldered portions for flash prevention
US6813828B2 (en) 2002-01-07 2004-11-09 Gel Pak L.L.C. Method for deconstructing an integrated circuit package using lapping
US6884663B2 (en) * 2002-01-07 2005-04-26 Delphon Industries, Llc Method for reconstructing an integrated circuit package using lapping
US20040194803A1 (en) * 2003-04-04 2004-10-07 Asm Technology Singapore Pte Ltd Cleaning of an electronic device
CN102956763A (zh) * 2011-08-29 2013-03-06 展晶科技(深圳)有限公司 发光二极管封装结构的制造方法
JP6625774B1 (ja) * 2019-02-20 2019-12-25 中央電子工業株式会社 中空パッケージ構造およびその製造方法、ならびに半導体装置およびその製造方法
CN112535961A (zh) * 2020-11-26 2021-03-23 河北航兴机械科技有限公司 一种去微小孔毛刺的装置
CN115672834B (zh) * 2022-09-13 2023-05-02 天水华洋电子科技股份有限公司 一种引线框架表面氧化点处理装置及其处理方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766657A (en) * 1980-10-14 1982-04-22 Noge Denki Kogyo:Kk Apparatus for automatically removing molded film before finish plating for external lead of molded semiconductor device
JPS5937055A (ja) * 1982-08-20 1984-02-29 Toshiba Corp 研摩材
JPS61152028A (ja) * 1984-12-26 1986-07-10 Hitachi Ltd レジンバリ除去装置
JPS6386529A (ja) * 1986-09-30 1988-04-16 Toshiba Corp 樹脂封止型半導体のバリ取り装置
US4907612A (en) * 1988-10-28 1990-03-13 National Semiconductor Corporation Universal material handling apparatus
US4968397A (en) * 1989-11-27 1990-11-06 Asher Reginald K Non-cyanide electrode cleaning process
JPH03274757A (ja) * 1990-03-23 1991-12-05 Mitsubishi Electric Corp ばり取り装置
JP3112022B2 (ja) * 1990-08-03 2000-11-27 三井化学株式会社 半導体装置の製造方法
US5186797A (en) * 1991-02-13 1993-02-16 Future Automation, Inc. Method and system for removing resin bleed from electronic components
JPH081115B2 (ja) * 1991-07-30 1996-01-10 新関西ベアリング株式会社 開度調整器のロック機構
US5318926A (en) * 1993-02-01 1994-06-07 Dlugokecki Joseph J Method for packaging an integrated circuit using a reconstructed plastic package
US5480607A (en) * 1993-03-22 1996-01-02 Hobson; Gerald R. Method and apparatus for molding plastic products with flash removed
JP2787907B2 (ja) * 1995-12-15 1998-08-20 日本電気株式会社 半導体装置用樹脂封止金型
RU2077611C1 (ru) * 1996-03-20 1997-04-20 Виталий Макарович Рябков Способ обработки поверхностей и устройство для его осуществления

Also Published As

Publication number Publication date
JP2760339B2 (ja) 1998-05-28
EP0794559B1 (de) 2004-02-04
US5956574A (en) 1999-09-21
DE69727410T2 (de) 2004-12-02
CA2199112C (en) 2001-05-01
EP0794559A3 (de) 1998-03-18
JPH09246299A (ja) 1997-09-19
AU709916B2 (en) 1999-09-09
CA2199112A1 (en) 1997-09-05
TW343367B (en) 1998-10-21
AU1505597A (en) 1997-09-11
KR100216164B1 (ko) 1999-08-16
KR970067811A (ko) 1997-10-13
EP0794559A2 (de) 1997-09-10

Similar Documents

Publication Publication Date Title
DE69508921D1 (de) Verfahren zum nachweis von staphylokokken
DE69719805D1 (de) Verfahren zum erzeugen von elastischen höckern
DE69711416D1 (de) Verfahren zum herstellen von aethylacetat
DE69827657D1 (de) Verfahren zum trennen von aromaten
DE69507607T2 (de) Verfahren zum herstellen von diamantfilmen
DE69522809T2 (de) Verfahren zum Verblasen von Kupferstein
DE69910464D1 (de) Verfahren zum Verbinden von unterschiedlichen Elementen
DE69718520D1 (de) Verfahren zum Schleifen von Verbundwerkstücken
DE69508293D1 (de) Verfahren zum Polieren von Metallbändern
DE69502997D1 (de) Verfahren zum Herstellen von Bürsten
DE69522828D1 (de) Verfahren zum entmetallieren von raffinerieeizätzen
DE59812633D1 (de) Verfahren zum Verbinden von Bauteilen
DE69522745D1 (de) Verfahren zum Abbau von Polysiloxanen
DE69727410D1 (de) Verfahren zum Entgräten von Leiterrahmen
DE59500527D1 (de) Verfahren zum Stabilisieren von Organopolysiloxanen
DE69807090T2 (de) Verfahren zum spannen von schraubverbindungen
ATA62794A (de) Verfahren zum aufbereiten von feinerz
DE69914113D1 (de) Verfahren zum Polieren von Werkstücken
DE69504476T2 (de) Verfahren zum herstellen von polyflouroxetanen
DE59703015D1 (de) Verfahren zum herstellen von eisenschwamm
DE69925643D1 (de) Verfahren zum gleichzeitigen abfasen von komplementären linsen
DE59704812D1 (de) Verfahren zum herstellen von metallschwamm
DE69523638T2 (de) Verfahren zum Reinigen von Methacrylat
DE59504999D1 (de) Verfahren zum aufbereiten von emballagen
DE59602226D1 (de) Verfahren zum Reinigen von ölbenetzten Bauteilen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

R082 Change of representative

Ref document number: 794559

Country of ref document: EP

Representative=s name: GLAWE DELFS MOLL - PARTNERSCHAFT VON PATENT- U, DE

R081 Change of applicant/patentee

Ref document number: 794559

Country of ref document: EP

Owner name: RENESAS ELECTRONICS CORPORATION, JP

Free format text: FORMER OWNER: NEC ELECTRONICS CORP., KAWASAKI, JP

Effective date: 20120828

R082 Change of representative

Ref document number: 794559

Country of ref document: EP

Representative=s name: GLAWE DELFS MOLL - PARTNERSCHAFT VON PATENT- U, DE

Effective date: 20120828