DE69721376D1 - Verbesserungen in oder in Bezug auf Halbleiteranordnungen - Google Patents

Verbesserungen in oder in Bezug auf Halbleiteranordnungen

Info

Publication number
DE69721376D1
DE69721376D1 DE69721376T DE69721376T DE69721376D1 DE 69721376 D1 DE69721376 D1 DE 69721376D1 DE 69721376 T DE69721376 T DE 69721376T DE 69721376 T DE69721376 T DE 69721376T DE 69721376 D1 DE69721376 D1 DE 69721376D1
Authority
DE
Germany
Prior art keywords
respect
semiconductor devices
semiconductor
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69721376T
Other languages
English (en)
Other versions
DE69721376T2 (de
Inventor
Peter S Mcanally
Jeffrey A Mckee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69721376D1 publication Critical patent/DE69721376D1/de
Application granted granted Critical
Publication of DE69721376T2 publication Critical patent/DE69721376T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
DE69721376T 1996-05-20 1997-05-20 Verbesserungen in oder in Bezug auf Halbleiteranordnungen Expired - Fee Related DE69721376T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1799596P 1996-05-20 1996-05-20
US17995P 1996-05-20

Publications (2)

Publication Number Publication Date
DE69721376D1 true DE69721376D1 (de) 2003-06-05
DE69721376T2 DE69721376T2 (de) 2004-04-01

Family

ID=21785697

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69721376T Expired - Fee Related DE69721376T2 (de) 1996-05-20 1997-05-20 Verbesserungen in oder in Bezug auf Halbleiteranordnungen

Country Status (5)

Country Link
US (1) US5960304A (de)
EP (1) EP0809281B1 (de)
JP (1) JPH1050841A (de)
DE (1) DE69721376T2 (de)
TW (1) TW370693B (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6103593A (en) * 1998-02-13 2000-08-15 Advanced Micro Devices, Inc. Method and system for providing a contact on a semiconductor device
KR100292820B1 (ko) * 1998-08-17 2001-07-12 윤종용 반도체 장치의 패드 제조 방법
US6319822B1 (en) * 1998-10-01 2001-11-20 Taiwan Semiconductor Manufacturing Company Process for forming an integrated contact or via
JP3436221B2 (ja) 1999-03-15 2003-08-11 ソニー株式会社 半導体装置の製造方法
US6207573B1 (en) * 1999-05-19 2001-03-27 Infineon Technologies North America Corp. Differential trench open process
US6365509B1 (en) * 2000-05-31 2002-04-02 Advanced Micro Devices, Inc. Semiconductor manufacturing method using a dielectric photomask
US6407002B1 (en) * 2000-08-10 2002-06-18 Taiwan Semiconductor Manufacturing Company Partial resist free approach in contact etch to improve W-filling

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4560436A (en) * 1984-07-02 1985-12-24 Motorola, Inc. Process for etching tapered polyimide vias
IT1225623B (it) * 1988-10-20 1990-11-22 Sgs Thomson Microelectronics Formazione di contatti autoallineati senza l'impiego di una relativa maschera
WO1991010261A1 (en) * 1990-01-04 1991-07-11 International Business Machines Corporation Semiconductor interconnect structure utilizing a polyimide insulator
US4997790A (en) * 1990-08-13 1991-03-05 Motorola, Inc. Process for forming a self-aligned contact structure
US5302240A (en) * 1991-01-22 1994-04-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
KR960000375B1 (ko) * 1991-01-22 1996-01-05 가부시끼가이샤 도시바 반도체장치의 제조방법
US5200358A (en) * 1991-11-15 1993-04-06 At&T Bell Laboratories Integrated circuit with planar dielectric layer
US5270263A (en) * 1991-12-20 1993-12-14 Micron Technology, Inc. Process for depositing aluminum nitride (AlN) using nitrogen plasma sputtering
US5229326A (en) * 1992-06-23 1993-07-20 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
JP2925416B2 (ja) * 1992-11-09 1999-07-28 株式会社東芝 半導体集積回路装置の製造方法
JP3181741B2 (ja) * 1993-01-11 2001-07-03 富士通株式会社 半導体装置の製造方法
US5439846A (en) * 1993-12-17 1995-08-08 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
JP2765478B2 (ja) * 1994-03-30 1998-06-18 日本電気株式会社 半導体装置およびその製造方法
US5466639A (en) * 1994-10-06 1995-11-14 Micron Semiconductor, Inc. Double mask process for forming trenches and contacts during the formation of a semiconductor memory device
JP3402022B2 (ja) * 1995-11-07 2003-04-28 三菱電機株式会社 半導体装置の製造方法
US5661083A (en) * 1996-01-30 1997-08-26 Integrated Device Technology, Inc. Method for via formation with reduced contact resistance

Also Published As

Publication number Publication date
EP0809281B1 (de) 2003-05-02
EP0809281A3 (de) 1997-12-10
EP0809281A2 (de) 1997-11-26
JPH1050841A (ja) 1998-02-20
DE69721376T2 (de) 2004-04-01
TW370693B (en) 1999-09-21
US5960304A (en) 1999-09-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee