DE69712113T2 - Speichertester mit datenkompression - Google Patents

Speichertester mit datenkompression

Info

Publication number
DE69712113T2
DE69712113T2 DE69712113T DE69712113T DE69712113T2 DE 69712113 T2 DE69712113 T2 DE 69712113T2 DE 69712113 T DE69712113 T DE 69712113T DE 69712113 T DE69712113 T DE 69712113T DE 69712113 T2 DE69712113 T2 DE 69712113T2
Authority
DE
Germany
Prior art keywords
data
test
memory
display
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69712113T
Other languages
German (de)
English (en)
Other versions
DE69712113D1 (de
Inventor
J. Brown
F. Donaldson
B. Gage
Alexander Joffe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Application granted granted Critical
Publication of DE69712113D1 publication Critical patent/DE69712113D1/de
Publication of DE69712113T2 publication Critical patent/DE69712113T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31935—Storing data, e.g. failure memory
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31912—Tester/user interface
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69712113T 1996-11-19 1997-11-18 Speichertester mit datenkompression Expired - Lifetime DE69712113T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/752,414 US6360340B1 (en) 1996-11-19 1996-11-19 Memory tester with data compression
PCT/US1997/020997 WO1998022951A1 (en) 1996-11-19 1997-11-18 Memory tester with data compression

Publications (2)

Publication Number Publication Date
DE69712113D1 DE69712113D1 (de) 2002-05-23
DE69712113T2 true DE69712113T2 (de) 2002-11-21

Family

ID=25026221

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69712113T Expired - Lifetime DE69712113T2 (de) 1996-11-19 1997-11-18 Speichertester mit datenkompression

Country Status (6)

Country Link
US (1) US6360340B1 (enExample)
EP (1) EP1016089B1 (enExample)
JP (1) JP2001504626A (enExample)
KR (1) KR100516428B1 (enExample)
DE (1) DE69712113T2 (enExample)
WO (1) WO1998022951A1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW473728B (en) * 1999-07-22 2002-01-21 Koninkl Philips Electronics Nv A method for testing a memory array and a memory-based device so testable with a fault response signalizing mode for when finding predetermined correspondence between fault patterns signalizing one such fault pattern only in the form of a compressed resp
US6629282B1 (en) * 1999-11-05 2003-09-30 Advantest Corp. Module based flexible semiconductor test system
US6718487B1 (en) * 2000-06-27 2004-04-06 Infineon Technologies North America Corp. Method for high speed testing with low speed semiconductor test equipment
KR100723464B1 (ko) * 2000-11-29 2007-06-04 삼성전자주식회사 프레임비트를 이용하여 테스트모드의 경우의 수를확장하는 테스트모드 설정회로
US6577156B2 (en) * 2000-12-05 2003-06-10 International Business Machines Corporation Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox
US6834364B2 (en) * 2001-04-19 2004-12-21 Agilent Technologies, Inc. Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences
CA2348799A1 (fr) * 2001-05-22 2002-11-22 Marcel Blais Appareil d'essai de composants electroniques
KR100459698B1 (ko) * 2002-02-08 2004-12-04 삼성전자주식회사 병렬검사되는 개수를 증가시키는 반도체 소자의 전기적검사방법
US7139943B2 (en) * 2002-03-29 2006-11-21 Infineon Technologies Ag Method and apparatus for providing adjustable latency for test mode compression
US7392434B2 (en) * 2002-10-21 2008-06-24 Zeroplus Technology Co., Ltd. Logic analyzer data processing method
CA2503342A1 (en) * 2002-10-21 2004-05-06 Zeroplus Technology Co., Ltd. Logic analyzer data processing method
EP1416641A1 (en) * 2002-10-30 2004-05-06 STMicroelectronics S.r.l. Method for compressing high repetitivity data, in particular data used in memory device testing
US7493534B2 (en) * 2003-08-29 2009-02-17 Hewlett-Packard Development Company, L.P. Memory error ranking
US7472330B2 (en) * 2003-11-26 2008-12-30 Samsung Electronics Co., Ltd. Magnetic memory which compares compressed fault maps
US7484065B2 (en) 2004-04-20 2009-01-27 Hewlett-Packard Development Company, L.P. Selective memory allocation
US20060236185A1 (en) * 2005-04-04 2006-10-19 Ronald Baker Multiple function results using single pattern and method
KR100747370B1 (ko) 2005-04-21 2007-08-07 제로플러스 테크날러지 코포레이션 엘티디 논리분석기 데이터 처리 방법
US20070266283A1 (en) * 2006-05-01 2007-11-15 Nec Laboratories America, Inc. Method and Apparatus for Testing an Integrated Circuit
US7596729B2 (en) * 2006-06-30 2009-09-29 Micron Technology, Inc. Memory device testing system and method using compressed fail data
US8059547B2 (en) * 2008-12-08 2011-11-15 Advantest Corporation Test apparatus and test method
US8743702B2 (en) * 2008-12-08 2014-06-03 Advantest Corporation Test apparatus and test method
KR20150008707A (ko) 2013-07-15 2015-01-23 삼성전자주식회사 독출 데이터를 마스킹하는 메모리 장치 및 이의 테스트 방법
JP6715198B2 (ja) 2017-02-20 2020-07-01 キオクシア株式会社 メモリ検査装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59180898A (ja) * 1983-03-31 1984-10-15 Hitachi Ltd 不良ビット救済方法
DE3482901D1 (de) * 1983-05-11 1990-09-13 Hitachi Ltd Pruefgeraet fuer redundanzspeicher.
US4876685A (en) * 1987-06-08 1989-10-24 Teradyne, Inc. Failure information processing in automatic memory tester
EP0424612A3 (en) * 1989-08-30 1992-03-11 International Business Machines Corporation Apparatus and method for real time data error capture and compression for redundancy analysis of a memory
US5173906A (en) 1990-08-31 1992-12-22 Dreibelbis Jeffrey H Built-in self test for integrated circuits
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
CA2180240A1 (en) * 1994-01-14 1995-07-20 Charles K. Chui Boundary-spline-wavelet compression for video images
JP3552175B2 (ja) * 1995-05-17 2004-08-11 株式会社アドバンテスト フェイルメモリ装置

Also Published As

Publication number Publication date
US6360340B1 (en) 2002-03-19
EP1016089A1 (en) 2000-07-05
EP1016089B1 (en) 2002-04-17
JP2001504626A (ja) 2001-04-03
WO1998022951A1 (en) 1998-05-28
DE69712113D1 (de) 2002-05-23
KR100516428B1 (ko) 2005-09-22
KR20000053363A (ko) 2000-08-25

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