DE69630427T2 - Bus-Halteschaltung - Google Patents
Bus-Halteschaltung Download PDFInfo
- Publication number
- DE69630427T2 DE69630427T2 DE69630427T DE69630427T DE69630427T2 DE 69630427 T2 DE69630427 T2 DE 69630427T2 DE 69630427 T DE69630427 T DE 69630427T DE 69630427 T DE69630427 T DE 69630427T DE 69630427 T2 DE69630427 T2 DE 69630427T2
- Authority
- DE
- Germany
- Prior art keywords
- channel transistor
- bus
- supply voltage
- hold circuit
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000872 buffer Substances 0.000 description 21
- 238000010586 diagram Methods 0.000 description 19
- 230000004048 modification Effects 0.000 description 19
- 238000012986 modification Methods 0.000 description 19
- 230000003071 parasitic effect Effects 0.000 description 14
- 238000012360 testing method Methods 0.000 description 11
- 230000008859 change Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 101150101567 pat-2 gene Proteins 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Small-Scale Networks (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22421895A JP3192937B2 (ja) | 1995-08-31 | 1995-08-31 | バスホールド回路 |
| JP22421895 | 1995-08-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69630427D1 DE69630427D1 (de) | 2003-11-27 |
| DE69630427T2 true DE69630427T2 (de) | 2004-07-29 |
Family
ID=16810372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69630427T Expired - Lifetime DE69630427T2 (de) | 1995-08-31 | 1996-08-29 | Bus-Halteschaltung |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5739702A (enExample) |
| EP (1) | EP0762648B1 (enExample) |
| JP (1) | JP3192937B2 (enExample) |
| KR (1) | KR100241201B1 (enExample) |
| DE (1) | DE69630427T2 (enExample) |
| TW (1) | TW305956B (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11317657A (ja) | 1998-05-06 | 1999-11-16 | Toshiba Corp | トランスミッション・ゲート回路 |
| TW511335B (en) | 1998-06-09 | 2002-11-21 | Mitsubishi Electric Corp | Integrated circuit |
| US6191607B1 (en) * | 1998-09-16 | 2001-02-20 | Cypress Semiconductor Corporation | Programmable bus hold circuit and method of using the same |
| JP4119062B2 (ja) * | 1999-10-25 | 2008-07-16 | 日本テキサス・インスツルメンツ株式会社 | 終端回路 |
| US6512406B1 (en) * | 1999-12-16 | 2003-01-28 | Intel Corporation | Backgate biased synchronizing latch |
| US6504401B1 (en) * | 2001-11-30 | 2003-01-07 | Xilinx, Inc. | Configurable bus hold circuit with low leakage current |
| US7064593B2 (en) * | 2004-09-20 | 2006-06-20 | Texas Instruments Incorporated | Bus-hold circuit |
| JP4768642B2 (ja) * | 2007-01-17 | 2011-09-07 | エヌイーシーコンピュータテクノ株式会社 | トライステートバス回路 |
| FR3062920B1 (fr) * | 2017-02-16 | 2021-06-25 | Spryngs | Circuit de polarisation active et faible consommation d'une entree haute impedance |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5516539A (en) * | 1978-07-20 | 1980-02-05 | Nec Corp | Level shifter circuit |
| US4484088A (en) * | 1983-02-04 | 1984-11-20 | General Electric Company | CMOS Four-transistor reset/set latch |
| US4558237A (en) * | 1984-03-30 | 1985-12-10 | Honeywell Inc. | Logic families interface circuit and having a CMOS latch for controlling hysteresis |
| US5498976A (en) * | 1990-10-26 | 1996-03-12 | Acer Incorporated | Parallel buffer/driver configuration between data sending terminal and data receiving terminal |
| JPH073958B2 (ja) * | 1992-01-31 | 1995-01-18 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 終端回路 |
| JPH0685653A (ja) * | 1992-05-06 | 1994-03-25 | Sgs Thomson Microelectron Inc | バスキーパ特徴を有するレシーバ回路 |
| US5227677A (en) * | 1992-06-10 | 1993-07-13 | International Business Machines Corporation | Zero power transmission line terminator |
| US5347177A (en) * | 1993-01-14 | 1994-09-13 | Lipp Robert J | System for interconnecting VLSI circuits with transmission line characteristics |
| US5469473A (en) * | 1994-04-15 | 1995-11-21 | Texas Instruments Incorporated | Transceiver circuit with transition detection |
| JP3625881B2 (ja) * | 1994-12-20 | 2005-03-02 | 株式会社ルネサステクノロジ | バスシステム及びバスセンスアンプ |
-
1995
- 1995-08-31 JP JP22421895A patent/JP3192937B2/ja not_active Expired - Fee Related
-
1996
- 1996-08-29 EP EP96113838A patent/EP0762648B1/en not_active Expired - Lifetime
- 1996-08-29 US US08/704,995 patent/US5739702A/en not_active Expired - Lifetime
- 1996-08-29 DE DE69630427T patent/DE69630427T2/de not_active Expired - Lifetime
- 1996-08-30 KR KR1019960036655A patent/KR100241201B1/ko not_active Expired - Lifetime
- 1996-09-19 TW TW085111475A patent/TW305956B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0969770A (ja) | 1997-03-11 |
| US5739702A (en) | 1998-04-14 |
| DE69630427D1 (de) | 2003-11-27 |
| JP3192937B2 (ja) | 2001-07-30 |
| KR100241201B1 (ko) | 2000-02-01 |
| TW305956B (enExample) | 1997-05-21 |
| EP0762648B1 (en) | 2003-10-22 |
| EP0762648A2 (en) | 1997-03-12 |
| KR970013701A (ko) | 1997-03-29 |
| EP0762648A3 (en) | 1999-01-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |