DE69528098T2 - Verfahren zur Isolierung activer Zonen in einem Halbleitersubstrat mittels untiefen, nicht breiten Graben - Google Patents

Verfahren zur Isolierung activer Zonen in einem Halbleitersubstrat mittels untiefen, nicht breiten Graben

Info

Publication number
DE69528098T2
DE69528098T2 DE69528098T DE69528098T DE69528098T2 DE 69528098 T2 DE69528098 T2 DE 69528098T2 DE 69528098 T DE69528098 T DE 69528098T DE 69528098 T DE69528098 T DE 69528098T DE 69528098 T2 DE69528098 T2 DE 69528098T2
Authority
DE
Germany
Prior art keywords
shallow
semiconductor substrate
active zones
isolating active
wide trenches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69528098T
Other languages
English (en)
Other versions
DE69528098D1 (de
Inventor
Maryse Paoli
Pierre Brouquet
Michel Haond
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Original Assignee
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Application granted granted Critical
Publication of DE69528098D1 publication Critical patent/DE69528098D1/de
Publication of DE69528098T2 publication Critical patent/DE69528098T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/133—Reflow oxides and glasses

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
DE69528098T 1994-03-11 1995-03-10 Verfahren zur Isolierung activer Zonen in einem Halbleitersubstrat mittels untiefen, nicht breiten Graben Expired - Lifetime DE69528098T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9402870A FR2717306B1 (fr) 1994-03-11 1994-03-11 Procédé d'isolement de zones actives d'un substrat semi-conducteur par tranchées peu profondes, notamment étroites, et dispositif correspondant.

Publications (2)

Publication Number Publication Date
DE69528098D1 DE69528098D1 (de) 2002-10-17
DE69528098T2 true DE69528098T2 (de) 2003-06-05

Family

ID=9460953

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69528098T Expired - Lifetime DE69528098T2 (de) 1994-03-11 1995-03-10 Verfahren zur Isolierung activer Zonen in einem Halbleitersubstrat mittels untiefen, nicht breiten Graben

Country Status (5)

Country Link
US (1) US5641704A (de)
EP (1) EP0673061B1 (de)
JP (1) JPH0846027A (de)
DE (1) DE69528098T2 (de)
FR (1) FR2717306B1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5863828A (en) * 1996-09-25 1999-01-26 National Semiconductor Corporation Trench planarization technique
US5880007A (en) * 1997-09-30 1999-03-09 Siemens Aktiengesellschaft Planarization of a non-conformal device layer in semiconductor fabrication
US5989978A (en) * 1998-07-16 1999-11-23 Chartered Semiconductor Manufacturing, Ltd. Shallow trench isolation of MOSFETS with reduced corner parasitic currents
US6121078A (en) * 1998-09-17 2000-09-19 International Business Machines Corporation Integrated circuit planarization and fill biasing design method
US6239002B1 (en) 1998-10-19 2001-05-29 Taiwan Semiconductor Manufacturing Company Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer
US5998279A (en) * 1998-11-27 1999-12-07 Vanguard International Semiconductor Corporation Manufacture of a shallow trench isolation device by exposing negative photoresist to increased exposure energy and chemical mechanical planarization
US6037238A (en) * 1999-01-04 2000-03-14 Vanguard International Semiconductor Corporation Process to reduce defect formation occurring during shallow trench isolation formation
US6180489B1 (en) 1999-04-12 2001-01-30 Vanguard International Semiconductor Corporation Formation of finely controlled shallow trench isolation for ULSI process
US6498061B2 (en) 2000-12-06 2002-12-24 International Business Machines Corporation Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation
JP3703799B2 (ja) * 2002-12-13 2005-10-05 沖電気工業株式会社 残膜厚分布の推定方法、残膜厚分布の推定方法を用いたパターニング用マスク及び絶縁膜除去用マスクの修正方法、及び、修正されたパターニング用マスク及び絶縁膜除去用マスクを用いた半導体素子の製造方法
KR100614655B1 (ko) * 2005-01-13 2006-08-22 삼성전자주식회사 반도체 장치의 소자분리막을 형성하는 방법
US20060186509A1 (en) * 2005-02-24 2006-08-24 Honeywell International, Inc. Shallow trench isolation structure with active edge isolation
WO2016142588A1 (fr) * 2015-03-06 2016-09-15 Stmicroelectronics (Crolles 2) Sas Laser germanium sur silicium en technologie cmos

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
JPS59181640A (ja) * 1983-03-31 1984-10-16 Fujitsu Ltd 半導体装置の製造方法
US4543706A (en) * 1984-02-24 1985-10-01 Gte Laboratories Incorporated Fabrication of junction field effect transistor with filled grooves
US4571819A (en) * 1984-11-01 1986-02-25 Ncr Corporation Method for forming trench isolation structures
JPS62216261A (ja) * 1986-03-17 1987-09-22 Sony Corp 半導体装置の製造方法
JPS62252050A (ja) * 1986-04-25 1987-11-02 Matsushita Electric Ind Co Ltd 画像表示装置用真空容器
NL8701717A (nl) * 1987-07-21 1989-02-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw.
US4954459A (en) * 1988-05-12 1990-09-04 Advanced Micro Devices, Inc. Method of planarization of topologies in integrated circuit structures
US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
US5094972A (en) * 1990-06-14 1992-03-10 National Semiconductor Corp. Means of planarizing integrated circuits with fully recessed isolation dielectric
JPH0513566A (ja) * 1991-07-01 1993-01-22 Toshiba Corp 半導体装置の製造方法
JPH0574927A (ja) * 1991-09-13 1993-03-26 Nec Corp 半導体装置の製造方法
JPH05304219A (ja) * 1992-04-27 1993-11-16 Kawasaki Steel Corp 半導体装置における絶縁層の形成方法
KR950002951B1 (ko) * 1992-06-18 1995-03-28 현대전자산업 주식회사 트렌치 소자분리막 제조방법
US5275965A (en) * 1992-11-25 1994-01-04 Micron Semiconductor, Inc. Trench isolation using gated sidewalls
US5472904A (en) * 1994-03-02 1995-12-05 Micron Technology, Inc. Thermal trench isolation
US5492858A (en) * 1994-04-20 1996-02-20 Digital Equipment Corporation Shallow trench isolation process for high aspect ratio trenches

Also Published As

Publication number Publication date
JPH0846027A (ja) 1996-02-16
US5641704A (en) 1997-06-24
FR2717306A1 (fr) 1995-09-15
EP0673061A1 (de) 1995-09-20
FR2717306B1 (fr) 1996-07-19
EP0673061B1 (de) 2002-09-11
DE69528098D1 (de) 2002-10-17

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