DE69521257D1 - Fliessband-Halbleiterspeicheranordnung, die Zeitverlust beim Datenzugriff aufgrund des Unterschieds zwischen Fliessbandstufen eliminiert - Google Patents
Fliessband-Halbleiterspeicheranordnung, die Zeitverlust beim Datenzugriff aufgrund des Unterschieds zwischen Fliessbandstufen eliminiertInfo
- Publication number
- DE69521257D1 DE69521257D1 DE69521257T DE69521257T DE69521257D1 DE 69521257 D1 DE69521257 D1 DE 69521257D1 DE 69521257 T DE69521257 T DE 69521257T DE 69521257 T DE69521257 T DE 69521257T DE 69521257 D1 DE69521257 D1 DE 69521257D1
- Authority
- DE
- Germany
- Prior art keywords
- conveyor belt
- difference
- semiconductor memory
- data access
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6232732A JP3013714B2 (ja) | 1994-09-28 | 1994-09-28 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69521257D1 true DE69521257D1 (de) | 2001-07-19 |
DE69521257T2 DE69521257T2 (de) | 2002-04-25 |
Family
ID=16943919
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69521257T Expired - Fee Related DE69521257T2 (de) | 1994-09-28 | 1995-09-26 | Fliessband-Halbleiterspeicheranordnung, die Zeitverlust beim Datenzugriff aufgrund des Unterschieds zwischen Fliessbandstufen eliminiert |
Country Status (5)
Country | Link |
---|---|
US (1) | US5579267A (de) |
EP (1) | EP0704848B1 (de) |
JP (1) | JP3013714B2 (de) |
KR (1) | KR0170006B1 (de) |
DE (1) | DE69521257T2 (de) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0883491A (ja) * | 1994-09-13 | 1996-03-26 | Mitsubishi Denki Eng Kk | データ読出回路 |
JPH08263985A (ja) * | 1995-03-24 | 1996-10-11 | Nec Corp | 半導体記憶装置 |
WO1997008614A1 (en) * | 1995-08-28 | 1997-03-06 | Motorola Inc. | Method and system for performing an l1 norm operation |
JP3252678B2 (ja) * | 1995-10-20 | 2002-02-04 | 日本電気株式会社 | 同期式半導体メモリ |
JP2904076B2 (ja) * | 1995-11-10 | 1999-06-14 | 日本電気株式会社 | 半導体記憶装置 |
JP3183321B2 (ja) * | 1995-11-10 | 2001-07-09 | 日本電気株式会社 | 半導体記憶装置 |
JP3192077B2 (ja) * | 1996-01-30 | 2001-07-23 | 日本電気株式会社 | 半導体記憶装置 |
US5784705A (en) * | 1996-07-15 | 1998-07-21 | Mosys, Incorporated | Method and structure for performing pipeline burst accesses in a semiconductor memory |
JP4090088B2 (ja) * | 1996-09-17 | 2008-05-28 | 富士通株式会社 | 半導体装置システム及び半導体装置 |
JPH10208470A (ja) * | 1997-01-17 | 1998-08-07 | Nec Corp | 同期型半導体記憶装置 |
US5920518A (en) * | 1997-02-11 | 1999-07-06 | Micron Technology, Inc. | Synchronous clock generator including delay-locked loop |
US5940608A (en) | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US5946244A (en) | 1997-03-05 | 1999-08-31 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US6173432B1 (en) | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
US5940609A (en) * | 1997-08-29 | 1999-08-17 | Micorn Technology, Inc. | Synchronous clock generator including a false lock detector |
US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
CA2805213A1 (en) * | 1998-04-01 | 1999-10-01 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
WO1999050852A1 (en) | 1998-04-01 | 1999-10-07 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6470060B1 (en) | 1999-03-01 | 2002-10-22 | Micron Technology, Inc. | Method and apparatus for generating a phase dependent control signal |
US6615307B1 (en) * | 2000-05-10 | 2003-09-02 | Micron Technology, Inc. | Flash with consistent latency for read operations |
JP4480855B2 (ja) * | 2000-06-08 | 2010-06-16 | 富士通マイクロエレクトロニクス株式会社 | 半導体デバイスを含むモジュール、及びモジュールを含むシステム |
KR100872213B1 (ko) | 2000-07-07 | 2008-12-05 | 모사이드 테크놀로지스, 인코포레이티드 | 메모리 소자에서의 읽기 명령 수행 방법 |
US6359827B1 (en) * | 2000-08-22 | 2002-03-19 | Micron Technology, Inc. | Method of constructing a very wide, very fast distributed memory |
US6912626B1 (en) | 2000-08-31 | 2005-06-28 | Micron Technology, Inc. | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner |
US6349056B1 (en) | 2000-12-28 | 2002-02-19 | Sandisk Corporation | Method and structure for efficient data verification operation for non-volatile memories |
US6788593B2 (en) * | 2001-02-28 | 2004-09-07 | Rambus, Inc. | Asynchronous, high-bandwidth memory component using calibrated timing elements |
US6801989B2 (en) | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
US7051264B2 (en) * | 2001-11-14 | 2006-05-23 | Monolithic System Technology, Inc. | Error correcting memory and method of operating same |
US6751129B1 (en) * | 2002-05-21 | 2004-06-15 | Sandisk Corporation | Efficient read, write methods for multi-state memory |
US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
US7392456B2 (en) * | 2004-11-23 | 2008-06-24 | Mosys, Inc. | Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory |
US20060206744A1 (en) * | 2005-03-08 | 2006-09-14 | Nec Laboratories America, Inc. | Low-power high-throughput streaming computations |
KR100906644B1 (ko) | 2007-12-27 | 2009-07-07 | 주식회사 하이닉스반도체 | 반도체 메모리장치 |
JP7187721B2 (ja) * | 2020-06-19 | 2022-12-12 | 華邦電子股▲ふん▼有限公司 | メモリデバイス及びその動作方法 |
JP2022000832A (ja) * | 2020-06-19 | 2022-01-04 | 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. | メモリデバイス及びその動作方法 |
US11417390B2 (en) | 2020-07-07 | 2022-08-16 | Winbond Electronics Corp. | Memory device and operation method thereof |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61148692A (ja) | 1984-12-24 | 1986-07-07 | Nippon Telegr & Teleph Corp <Ntt> | 記憶装置 |
JPH02172097A (ja) * | 1988-12-23 | 1990-07-03 | Nec Corp | メモリ |
JP3178859B2 (ja) * | 1991-06-05 | 2001-06-25 | 株式会社東芝 | ランダムアクセスメモリ装置およびそのパイプライン・ページモード制御方法 |
JP2830594B2 (ja) * | 1992-03-26 | 1998-12-02 | 日本電気株式会社 | 半導体メモリ装置 |
JPH06187787A (ja) * | 1992-12-17 | 1994-07-08 | Hitachi Ltd | 半導体記憶装置とそのパイプライン動作制御方法 |
US5471607A (en) * | 1993-04-22 | 1995-11-28 | Analog Devices, Inc. | Multi-phase multi-access pipeline memory system |
-
1994
- 1994-09-28 JP JP6232732A patent/JP3013714B2/ja not_active Expired - Lifetime
-
1995
- 1995-09-26 DE DE69521257T patent/DE69521257T2/de not_active Expired - Fee Related
- 1995-09-26 EP EP95115163A patent/EP0704848B1/de not_active Expired - Lifetime
- 1995-09-26 US US08/534,208 patent/US5579267A/en not_active Expired - Lifetime
- 1995-09-28 KR KR1019950032323A patent/KR0170006B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69521257T2 (de) | 2002-04-25 |
JPH0896573A (ja) | 1996-04-12 |
EP0704848B1 (de) | 2001-06-13 |
KR0170006B1 (ko) | 1999-03-30 |
EP0704848A3 (de) | 1997-08-27 |
US5579267A (en) | 1996-11-26 |
EP0704848A2 (de) | 1996-04-03 |
JP3013714B2 (ja) | 2000-02-28 |
KR960012011A (ko) | 1996-04-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC CORP., TOKIO/TOKYO, JP Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8339 | Ceased/non-payment of the annual fee |