DE69520849D1 - Verfahren zur Herstellung eines bipolaren Transistors - Google Patents

Verfahren zur Herstellung eines bipolaren Transistors

Info

Publication number
DE69520849D1
DE69520849D1 DE69520849T DE69520849T DE69520849D1 DE 69520849 D1 DE69520849 D1 DE 69520849D1 DE 69520849 T DE69520849 T DE 69520849T DE 69520849 T DE69520849 T DE 69520849T DE 69520849 D1 DE69520849 D1 DE 69520849D1
Authority
DE
Germany
Prior art keywords
manufacturing
bipolar transistor
bipolar
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69520849T
Other languages
English (en)
Other versions
DE69520849T2 (de
Inventor
Edouard D Defresart
John W Steele
N David Theodore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69520849D1 publication Critical patent/DE69520849D1/de
Publication of DE69520849T2 publication Critical patent/DE69520849T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Recrystallisation Techniques (AREA)
DE69520849T 1994-02-28 1995-02-23 Verfahren zur Herstellung eines bipolaren Transistors Expired - Lifetime DE69520849T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/203,094 US5436180A (en) 1994-02-28 1994-02-28 Method for reducing base resistance in epitaxial-based bipolar transistor

Publications (2)

Publication Number Publication Date
DE69520849D1 true DE69520849D1 (de) 2001-06-13
DE69520849T2 DE69520849T2 (de) 2001-09-27

Family

ID=22752477

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69520849T Expired - Lifetime DE69520849T2 (de) 1994-02-28 1995-02-23 Verfahren zur Herstellung eines bipolaren Transistors

Country Status (5)

Country Link
US (1) US5436180A (de)
EP (1) EP0669647B1 (de)
JP (1) JP3530254B2 (de)
CN (1) CN1080930C (de)
DE (1) DE69520849T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274108A (ja) * 1995-03-31 1996-10-18 Toshiba Corp 半導体装置及びその製造方法
JP2937253B2 (ja) * 1996-01-17 1999-08-23 日本電気株式会社 半導体装置およびその製造方法
DE19840866B4 (de) * 1998-08-31 2005-02-03 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Verfahren zur Dotierung der externen Basisanschlußgebiete von Si-basierten Einfach-Polysilizium-npn-Bipolartransistoren
DE19845787A1 (de) * 1998-09-21 2000-03-23 Inst Halbleiterphysik Gmbh Bipolartransistor und Verfahren zu seiner Herstellung
DE19845793A1 (de) * 1998-09-21 2000-03-23 Inst Halbleiterphysik Gmbh Bipolartransistor und Verfahren zu seiner Herstellung
DE19845789A1 (de) * 1998-09-21 2000-03-23 Inst Halbleiterphysik Gmbh Bipolartransistor und Verfahren zu seiner Herstellung
US6531720B2 (en) 2001-04-19 2003-03-11 International Business Machines Corporation Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors
US7038298B2 (en) * 2003-06-24 2006-05-02 International Business Machines Corporation High fT and fmax bipolar transistor and method of making same
US7819981B2 (en) * 2004-10-26 2010-10-26 Advanced Technology Materials, Inc. Methods for cleaning ion implanter components
DE102004061327A1 (de) * 2004-12-11 2006-06-14 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Vertikaler Bipolartransistor
TWI552797B (zh) * 2005-06-22 2016-10-11 恩特葛瑞斯股份有限公司 整合式氣體混合用之裝置及方法
KR101297917B1 (ko) 2005-08-30 2013-08-27 어드밴스드 테크놀러지 머티리얼즈, 인코포레이티드 대안적인 불화 붕소 전구체를 이용한 붕소 이온 주입 방법,및 주입을 위한 대형 수소화붕소의 형성 방법
US20080179636A1 (en) * 2007-01-27 2008-07-31 International Business Machines Corporation N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers
CN101981661A (zh) 2008-02-11 2011-02-23 高级技术材料公司 在半导体处理系统中离子源的清洗
US20110021011A1 (en) 2009-07-23 2011-01-27 Advanced Technology Materials, Inc. Carbon materials for carbon implantation
US8598022B2 (en) 2009-10-27 2013-12-03 Advanced Technology Materials, Inc. Isotopically-enriched boron-containing compounds, and methods of making and using same
KR20200098716A (ko) 2012-02-14 2020-08-20 엔테그리스, 아이엔씨. 주입 빔 및 소스 수명 성능 개선을 위한 탄소 도판트 기체 및 동축류

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5539677A (en) * 1978-09-14 1980-03-19 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device and its manufacturing
JPS571225A (en) * 1980-06-03 1982-01-06 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS5831515A (ja) * 1981-08-18 1983-02-24 Nec Corp 半導体薄膜の製造方法
JPS6054452A (ja) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS63304657A (ja) * 1987-06-04 1988-12-12 Fujitsu Ltd 半導体装置の製造方法
US4914053A (en) * 1987-09-08 1990-04-03 Texas Instruments Incorporated Heteroepitaxial selective-area growth through insulator windows
JPH04314350A (ja) * 1991-04-12 1992-11-05 Hitachi Ltd 半導体集積回路装置の製造方法
US5273930A (en) * 1992-09-03 1993-12-28 Motorola, Inc. Method of forming a non-selective silicon-germanium epitaxial film

Also Published As

Publication number Publication date
EP0669647A3 (de) 1995-11-02
JP3530254B2 (ja) 2004-05-24
DE69520849T2 (de) 2001-09-27
CN1080930C (zh) 2002-03-13
US5436180A (en) 1995-07-25
EP0669647B1 (de) 2001-05-09
CN1111818A (zh) 1995-11-15
JPH07249637A (ja) 1995-09-26
EP0669647A2 (de) 1995-08-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: SCHUMACHER & WILLSAU, PATENTANWALTSSOZIETAET, 80335 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US