DE69712684D1 - Verfahren zur Herstellung eines Dünnschichttransistors - Google Patents

Verfahren zur Herstellung eines Dünnschichttransistors

Info

Publication number
DE69712684D1
DE69712684D1 DE69712684T DE69712684T DE69712684D1 DE 69712684 D1 DE69712684 D1 DE 69712684D1 DE 69712684 T DE69712684 T DE 69712684T DE 69712684 T DE69712684 T DE 69712684T DE 69712684 D1 DE69712684 D1 DE 69712684D1
Authority
DE
Germany
Prior art keywords
manufacturing
thin film
film transistor
transistor
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69712684T
Other languages
English (en)
Inventor
Gosain Dharam Pal
Miyako Nakagoe
Uesutoootaa Jiyonasan
Setsuo Usui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE69712684D1 publication Critical patent/DE69712684D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/88—Tunnel-effect diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/10—Lift-off masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
DE69712684T 1996-07-31 1997-07-09 Verfahren zur Herstellung eines Dünnschichttransistors Expired - Lifetime DE69712684D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8217754A JPH1050607A (ja) 1996-07-31 1996-07-31 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE69712684D1 true DE69712684D1 (de) 2002-06-27

Family

ID=16709230

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69712684T Expired - Lifetime DE69712684D1 (de) 1996-07-31 1997-07-09 Verfahren zur Herstellung eines Dünnschichttransistors

Country Status (5)

Country Link
US (3) US6093586A (de)
EP (1) EP0822581B1 (de)
JP (1) JPH1050607A (de)
KR (1) KR980012600A (de)
DE (1) DE69712684D1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100271813B1 (ko) * 1998-09-28 2000-11-15 구본준 실리콘 박막을 결정화하는 방법과 이를 이용한 박막트랜지스터및 그 제조방법
KR100353526B1 (ko) * 1999-06-18 2002-09-19 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP3645755B2 (ja) * 1999-09-17 2005-05-11 日本電気株式会社 薄膜トランジスタおよびその製造方法
TW452892B (en) * 2000-08-09 2001-09-01 Lin Jing Wei Re-crystallization method of polysilicon thin film of thin film transistor
US7300829B2 (en) * 2003-06-02 2007-11-27 Applied Materials, Inc. Low temperature process for TFT fabrication
KR100585873B1 (ko) * 2003-11-03 2006-06-07 엘지.필립스 엘시디 주식회사 폴리실리콘 액정표시소자 및 그 제조방법
KR100640213B1 (ko) * 2003-12-29 2006-10-31 엘지.필립스 엘시디 주식회사 폴리실리콘 액정표시소자 제조방법
TWI256515B (en) * 2004-04-06 2006-06-11 Quanta Display Inc Structure of LTPS-TFT and fabricating method thereof
TWI234288B (en) * 2004-07-27 2005-06-11 Au Optronics Corp Method for fabricating a thin film transistor and related circuits
TWI311213B (en) * 2004-12-24 2009-06-21 Au Optronics Corp Crystallizing method for forming poly-si films and thin film transistors using same
CN100388423C (zh) * 2005-01-17 2008-05-14 友达光电股份有限公司 多晶硅薄膜的制造方法以及由此获得的薄膜晶体管
US20060199314A1 (en) * 2005-03-02 2006-09-07 Chiun-Hung Chen Thin film transistor, and method of fabricating thin film transistor and pixel structure
KR101951707B1 (ko) * 2012-02-14 2019-02-26 삼성디스플레이 주식회사 기판의 평탄화 방법, 상기 평탄화 방법을 이용한 박막 트랜지스터의 제조 방법
US10038098B2 (en) * 2014-11-07 2018-07-31 Sakai Display Products Corporation Method for manufacturing thin film transistor, thin film transistor and display panel
US10243003B2 (en) * 2015-03-27 2019-03-26 Sakai Display Products Corporation Thin film transistor and display panel
CN118471789A (zh) * 2018-11-16 2024-08-09 玛特森技术公司 腔室上光以通过减少化学成分改善刻蚀均匀性

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2590409B1 (fr) * 1985-11-15 1987-12-11 Commissariat Energie Atomique Procede de fabrication d'un transistor en couches minces a grille auto-alignee par rapport au drain et a la source de celui-ci et transistor obtenu par le procede
JPH0622245B2 (ja) * 1986-05-02 1994-03-23 富士ゼロックス株式会社 薄膜トランジスタの製造方法
US5130263A (en) * 1990-04-17 1992-07-14 General Electric Company Method for photolithographically forming a selfaligned mask using back-side exposure and a non-specular reflecting layer
US5126701A (en) * 1990-12-28 1992-06-30 Raytheon Company Avalanche diode limiters
JP3255942B2 (ja) * 1991-06-19 2002-02-12 株式会社半導体エネルギー研究所 逆スタガ薄膜トランジスタの作製方法
EP0619601A2 (de) * 1993-04-05 1994-10-12 General Electric Company Selbstausrichtender Dünnschicht-Transistor mittels s.g. Lift-off Technik hergestellt
US5477073A (en) * 1993-08-20 1995-12-19 Casio Computer Co., Ltd. Thin film semiconductor device including a driver and a matrix circuit
US5391507A (en) * 1993-09-03 1995-02-21 General Electric Company Lift-off fabrication method for self-aligned thin film transistors
JPH09153458A (ja) * 1995-09-26 1997-06-10 Fujitsu Ltd 薄膜半導体装置およびその製造方法
JP3478012B2 (ja) * 1995-09-29 2003-12-10 ソニー株式会社 薄膜半導体装置の製造方法
US5637519A (en) * 1996-03-21 1997-06-10 Industrial Technology Research Institute Method of fabricating a lightly doped drain thin-film transistor

Also Published As

Publication number Publication date
EP0822581A3 (de) 1998-10-21
JPH1050607A (ja) 1998-02-20
EP0822581A2 (de) 1998-02-04
KR980012600A (ko) 1998-04-30
US6093586A (en) 2000-07-25
EP0822581B1 (de) 2002-05-22
US20050085099A1 (en) 2005-04-21
US20030207507A1 (en) 2003-11-06

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