DE69518997T2 - Digitale PLL-Schaltung - Google Patents

Digitale PLL-Schaltung

Info

Publication number
DE69518997T2
DE69518997T2 DE69518997T DE69518997T DE69518997T2 DE 69518997 T2 DE69518997 T2 DE 69518997T2 DE 69518997 T DE69518997 T DE 69518997T DE 69518997 T DE69518997 T DE 69518997T DE 69518997 T2 DE69518997 T2 DE 69518997T2
Authority
DE
Germany
Prior art keywords
pll circuit
digital pll
digital
circuit
pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69518997T
Other languages
English (en)
Other versions
DE69518997D1 (de
Inventor
Hidenori Minoda
Hiroyuki Matsuoka
Katsuaki Matsufuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP6308557A external-priority patent/JPH08167840A/ja
Priority claimed from JP6324307A external-priority patent/JPH0870249A/ja
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69518997D1 publication Critical patent/DE69518997D1/de
Publication of DE69518997T2 publication Critical patent/DE69518997T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
    • G11B19/20—Driving; Starting; Stopping; Control thereof
    • G11B19/24—Arrangements for providing constant relative speed between record carrier and head
    • G11B19/247—Arrangements for providing constant relative speed between record carrier and head using electrical means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE69518997T 1994-06-20 1995-05-29 Digitale PLL-Schaltung Expired - Fee Related DE69518997T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP13694294 1994-06-20
JP6308557A JPH08167840A (ja) 1994-12-13 1994-12-13 ディジタルｐｌｌ回路
JP6324307A JPH0870249A (ja) 1994-06-20 1994-12-27 ディジタルｐｌｌ回路

Publications (2)

Publication Number Publication Date
DE69518997D1 DE69518997D1 (de) 2000-11-09
DE69518997T2 true DE69518997T2 (de) 2001-03-01

Family

ID=27317369

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69518997T Expired - Fee Related DE69518997T2 (de) 1994-06-20 1995-05-29 Digitale PLL-Schaltung

Country Status (3)

Country Link
US (1) US5661425A (de)
EP (1) EP0689294B1 (de)
DE (1) DE69518997T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100190032B1 (ko) * 1996-03-30 1999-06-01 윤종용 Efm 데이타 복원용 클럭 발생방법 및 그 방법을 수행하는 위상동기 루프
US5914963A (en) * 1996-06-21 1999-06-22 Compaq Computer Corporation Clock skew reduction
GB2321142B (en) * 1997-01-13 2001-03-28 Plessey Semiconductors Ltd Frequency control arrangement
EP0854482B1 (de) * 1997-01-16 2004-03-31 SGS-THOMSON MICROELECTRONICS S.r.l. System und Methode zur Dekodierung des EFM- und EFM-Plus-Aufzeichnungsformats im Leseteil für optische Platten (CD und DVD)
KR100318842B1 (ko) * 1998-11-26 2002-04-22 윤종용 디지털위상제어루프에서의주파수검출방법
US6172538B1 (en) * 1999-01-06 2001-01-09 Chips & Technologies, L.L.C. Universal pulse synchronizer
JP3835945B2 (ja) * 1999-02-19 2006-10-18 富士通株式会社 ディジタルデータの伝送網におけるシステムクロック再生方法および装置
US7161998B2 (en) * 2001-01-24 2007-01-09 Broadcom Corporation Digital phase locked loop for regenerating the clock of an embedded signal
US7346122B1 (en) * 2002-08-21 2008-03-18 Weixun Cao Direct modulation of a power amplifier with adaptive digital predistortion
US8665929B1 (en) * 2011-05-12 2014-03-04 Valens Semiconductor Ltd. Method and device for deterministic timing acquiring and tracking

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4019153A (en) * 1974-10-07 1977-04-19 The Charles Stark Draper Laboratory, Inc. Digital phase-locked loop filter
JPS57173230A (en) * 1981-04-17 1982-10-25 Hitachi Ltd Phase synchronizing circuit
JPH0634308B2 (ja) * 1984-02-16 1994-05-02 松下電器産業株式会社 デイジタルオ−デイオデイスク再生装置
US4792768A (en) * 1987-11-06 1988-12-20 Hewlett-Packard Company Fast frequency settling signal generator utilizing a frequency locked-loop
JPH01303630A (ja) * 1988-05-31 1989-12-07 Matsushita Electric Ind Co Ltd デジタルディスク再生装置の同期検出装置
US4827225A (en) * 1988-06-13 1989-05-02 Unisys Corporation Fast locking phase-locked loop utilizing frequency estimation
JPH07101847B2 (ja) * 1988-10-21 1995-11-01 シャープ株式会社 デジタルフェイズロックドループ装置
JP2542097B2 (ja) * 1990-01-16 1996-10-09 パイオニア株式会社 クロック生成用ｐｌｌ回路を含む読取線速度可変型ディスク記録情報再生装置
JP2839620B2 (ja) * 1990-02-09 1998-12-16 パイオニア株式会社 クロック生成用ｐｌｌ回路
JPH03289820A (ja) * 1990-04-06 1991-12-19 Sony Corp ディジタルｐｌｌ
JP2689021B2 (ja) * 1990-11-27 1997-12-10 シャープ株式会社 データパルス発生装置
US5329560A (en) * 1992-05-19 1994-07-12 Sgs-Thomson Microelectronics, Inc. AGC circuit with non-linear gain for use in PLL circuit

Also Published As

Publication number Publication date
EP0689294A1 (de) 1995-12-27
EP0689294B1 (de) 2000-10-04
DE69518997D1 (de) 2000-11-09
US5661425A (en) 1997-08-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee