DE69514790D1 - Verfahren zur Einstellung der Schwellspannung einer Referenzspeicherzelle - Google Patents

Verfahren zur Einstellung der Schwellspannung einer Referenzspeicherzelle

Info

Publication number
DE69514790D1
DE69514790D1 DE69514790T DE69514790T DE69514790D1 DE 69514790 D1 DE69514790 D1 DE 69514790D1 DE 69514790 T DE69514790 T DE 69514790T DE 69514790 T DE69514790 T DE 69514790T DE 69514790 D1 DE69514790 D1 DE 69514790D1
Authority
DE
Germany
Prior art keywords
setting
memory cell
threshold voltage
reference memory
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69514790T
Other languages
English (en)
Other versions
DE69514790T2 (de
Inventor
Mauro Sali
Marco Dallabora
Marcello Carrera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69514790D1 publication Critical patent/DE69514790D1/de
Application granted granted Critical
Publication of DE69514790T2 publication Critical patent/DE69514790T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current
DE69514790T 1995-07-14 1995-07-14 Verfahren zur Einstellung der Schwellspannung einer Referenzspeicherzelle Expired - Fee Related DE69514790T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95830302A EP0753859B1 (de) 1995-07-14 1995-07-14 Verfahren zur Einstellung der Schwellspannung einer Referenzspeicherzelle

Publications (2)

Publication Number Publication Date
DE69514790D1 true DE69514790D1 (de) 2000-03-02
DE69514790T2 DE69514790T2 (de) 2000-08-03

Family

ID=8221971

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69514790T Expired - Fee Related DE69514790T2 (de) 1995-07-14 1995-07-14 Verfahren zur Einstellung der Schwellspannung einer Referenzspeicherzelle

Country Status (4)

Country Link
US (1) US5784314A (de)
EP (1) EP0753859B1 (de)
JP (1) JPH09128983A (de)
DE (1) DE69514790T2 (de)

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JPH11203881A (ja) * 1998-01-12 1999-07-30 Mitsubishi Electric Corp データ読み出し回路
KR100301817B1 (ko) 1999-06-29 2001-11-01 김영환 레퍼런스 메모리셀의 초기화 회로 및 그를 이용한 초기화 방법
US6629047B1 (en) * 2000-03-30 2003-09-30 Intel Corporation Method and apparatus for flash voltage detection and lockout
US6396741B1 (en) 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6490204B2 (en) * 2000-05-04 2002-12-03 Saifun Semiconductors Ltd. Programming and erasing methods for a reference cell of an NROM array
DE60037504T2 (de) 2000-05-31 2008-12-11 Stmicroelectronics S.R.L., Agrate Brianza Referenzzellenmatrixanordnung zum Datenlesen in einer nichtflüchtigen Speicheranordnung
EP1160794B1 (de) * 2000-05-31 2008-07-23 STMicroelectronics S.r.l. Schaltungsanordnung zum Programmieren von Daten in Referenzzellen einer nichtflüchtigen Multibitspeicheranordnung
US6697283B2 (en) 2001-01-03 2004-02-24 Micron Technology, Inc. Temperature and voltage compensated reference current generator
US6449190B1 (en) * 2001-01-17 2002-09-10 Advanced Micro Devices, Inc. Adaptive reference cells for a memory device
FR2820539B1 (fr) * 2001-02-02 2003-05-30 St Microelectronics Sa Procede et dispositif de rafraichissement de cellules de reference
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6643181B2 (en) 2001-10-24 2003-11-04 Saifun Semiconductors Ltd. Method for erasing a memory cell
US6975536B2 (en) * 2002-01-31 2005-12-13 Saifun Semiconductors Ltd. Mass storage array and methods for operation thereof
FR2836751A1 (fr) * 2002-02-11 2003-09-05 St Microelectronics Sa Cellule memoire a programmation unique non destructrice
FR2836752A1 (fr) * 2002-02-11 2003-09-05 St Microelectronics Sa Cellule memoire a programmation unique
FR2836749A1 (fr) * 2002-02-11 2003-09-05 St Microelectronics Sa Cellule memoire a programmation unique
FR2836750A1 (fr) * 2002-02-11 2003-09-05 St Microelectronics Sa Cellule memoire a programmation unique non destructrice
US6570797B1 (en) 2002-05-07 2003-05-27 Taiwan Semiconductor Manufacturing Company Design for test to emulate a read with worse case test pattern
US6917544B2 (en) * 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6711062B1 (en) * 2002-07-17 2004-03-23 Taiwan Semiconductor Manufacturing Company Erase method of split gate flash memory reference cells
US6826107B2 (en) * 2002-08-01 2004-11-30 Saifun Semiconductors Ltd. High voltage insertion in flash memory cards
US6963505B2 (en) * 2002-10-29 2005-11-08 Aifun Semiconductors Ltd. Method circuit and system for determining a reference voltage
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6992932B2 (en) 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US6967896B2 (en) * 2003-01-30 2005-11-22 Saifun Semiconductors Ltd Address scramble
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
ITTO20030115A1 (it) * 2003-02-17 2004-08-18 St Microelectronics Srl Metodo di soft-programmazione per un dispositivo di
US7142464B2 (en) * 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US6954393B2 (en) * 2003-09-16 2005-10-11 Saifun Semiconductors Ltd. Reading array cell with matched reference cell
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7652930B2 (en) 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7755938B2 (en) * 2004-04-19 2010-07-13 Saifun Semiconductors Ltd. Method for reading a memory array with neighbor effect cancellation
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7257025B2 (en) * 2004-12-09 2007-08-14 Saifun Semiconductors Ltd Method for reading non-volatile memory cells
WO2006071402A1 (en) * 2004-12-23 2006-07-06 Atmel Corporation System for performing fast testing during flash reference cell setting
ITMI20042473A1 (it) * 2004-12-23 2005-03-23 Atmel Corp Sistema per l'effettuazione di verifiche rapide durante la configurazione delle celle di riferimento flash
US8053812B2 (en) * 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7184313B2 (en) 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
US7804126B2 (en) 2005-07-18 2010-09-28 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7221138B2 (en) * 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7638835B2 (en) * 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7394698B1 (en) * 2006-12-28 2008-07-01 Macronix International Co., Ltd. Method and apparatus for adjusting a read reference level under dynamic power conditions
JP5166894B2 (ja) * 2008-01-30 2013-03-21 セイコーインスツル株式会社 半導体記憶装置
KR101105434B1 (ko) * 2009-03-02 2012-01-17 주식회사 하이닉스반도체 반도체 메모리 장치의 전류 감지 특성 평가 장치 및 방법
JP2011159355A (ja) * 2010-02-01 2011-08-18 Sanyo Electric Co Ltd 半導体記憶装置
US9437257B2 (en) * 2012-12-31 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Sensing circuit, memory device and data detecting method

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US5172338B1 (en) * 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
US5077691A (en) * 1989-10-23 1991-12-31 Advanced Micro Devices, Inc. Flash EEPROM array with negative gate voltage erase operation
JP3454520B2 (ja) * 1990-11-30 2003-10-06 インテル・コーポレーション フラッシュ記憶装置の書込み状態を確認する回路及びその方法
JPH0730000A (ja) * 1993-07-09 1995-01-31 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US5444656A (en) * 1994-06-02 1995-08-22 Intel Corporation Apparatus for fast internal reference cell trimming
US5481494A (en) * 1994-12-22 1996-01-02 Advanced Micro Devices, Inc. Method for tightening VT distribution of 5 volt-only flash EEPROMS

Also Published As

Publication number Publication date
EP0753859A1 (de) 1997-01-15
EP0753859B1 (de) 2000-01-26
JPH09128983A (ja) 1997-05-16
DE69514790T2 (de) 2000-08-03
US5784314A (en) 1998-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee