DE69426618D1 - Verfahren zum Ätzen von leitenden Schichten auf integrierten Schaltungen - Google Patents

Verfahren zum Ätzen von leitenden Schichten auf integrierten Schaltungen

Info

Publication number
DE69426618D1
DE69426618D1 DE69426618T DE69426618T DE69426618D1 DE 69426618 D1 DE69426618 D1 DE 69426618D1 DE 69426618 T DE69426618 T DE 69426618T DE 69426618 T DE69426618 T DE 69426618T DE 69426618 D1 DE69426618 D1 DE 69426618D1
Authority
DE
Germany
Prior art keywords
integrated circuits
conductive layers
etching conductive
etching
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69426618T
Other languages
English (en)
Inventor
Sailesh Chittipeddi
William Thomas Cochran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69426618D1 publication Critical patent/DE69426618D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
DE69426618T 1993-11-05 1994-10-26 Verfahren zum Ätzen von leitenden Schichten auf integrierten Schaltungen Expired - Lifetime DE69426618D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/147,368 US5439847A (en) 1993-11-05 1993-11-05 Integrated circuit fabrication with a raised feature as mask

Publications (1)

Publication Number Publication Date
DE69426618D1 true DE69426618D1 (de) 2001-03-01

Family

ID=22521295

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69426618T Expired - Lifetime DE69426618D1 (de) 1993-11-05 1994-10-26 Verfahren zum Ätzen von leitenden Schichten auf integrierten Schaltungen

Country Status (5)

Country Link
US (1) US5439847A (de)
EP (1) EP0652588B1 (de)
JP (1) JP3550195B2 (de)
KR (1) KR100330438B1 (de)
DE (1) DE69426618D1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976769A (en) * 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
KR100434132B1 (ko) * 1995-07-14 2004-09-08 텍사스 인스트루먼츠 인코포레이티드 중간층리쏘그래피
US6133146A (en) * 1996-05-09 2000-10-17 Scb Technologies, Inc. Semiconductor bridge device and method of making the same
US5950106A (en) * 1996-05-14 1999-09-07 Advanced Micro Devices, Inc. Method of patterning a metal substrate using spin-on glass as a hard mask
US6133635A (en) * 1997-06-30 2000-10-17 Philips Electronics North America Corp. Process for making self-aligned conductive via structures
US6281585B1 (en) 1997-06-30 2001-08-28 Philips Electronics North America Corporation Air gap dielectric in self-aligned via structures
US6420099B1 (en) * 1999-08-02 2002-07-16 Infineon Technologies Ag Tungsten hard mask for dry etching aluminum-containing layers
US6261967B1 (en) * 2000-02-09 2001-07-17 Infineon Technologies North America Corp. Easy to remove hard mask layer for semiconductor device fabrication
US6772692B2 (en) * 2000-05-24 2004-08-10 Lifesparc, Inc. Electro-explosive device with laminate bridge
US7538034B2 (en) * 2006-12-22 2009-05-26 Qimonda Ag Integrated circuit having a metal element

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4382827A (en) * 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
JPS6245071A (ja) * 1985-08-22 1987-02-27 Nec Corp 半導体装置の製造方法
JPS62241376A (ja) * 1986-04-11 1987-10-22 Seiko Epson Corp Mos型半導体装置の製造方法
US4676869A (en) * 1986-09-04 1987-06-30 American Telephone And Telegraph Company At&T Bell Laboratories Integrated circuits having stepped dielectric regions
US4728617A (en) * 1986-11-04 1988-03-01 Intel Corporation Method of fabricating a MOSFET with graded source and drain regions
US4820611A (en) * 1987-04-24 1989-04-11 Advanced Micro Devices, Inc. Titanium nitride as an antireflection coating on highly reflective layers for photolithography
JP2585064B2 (ja) * 1987-06-12 1997-02-26 ヒューレット・パッカード・カンパニー タングステン構造形成方法
US4786609A (en) * 1987-10-05 1988-11-22 North American Philips Corporation, Signetics Division Method of fabricating field-effect transistor utilizing improved gate sidewall spacers
KR910006093B1 (ko) * 1988-06-30 1991-08-12 삼성전자 주식회사 반도체 장치의 제조방법
EP0468071B1 (de) * 1990-07-25 1994-09-14 International Business Machines Corporation Methode zur Herstellung von mikromechanischen Sensoren für AFM/STM/MFM-Profilometrie und mikromechanischer AFM/STM/MFM-Sensorkopf
US5211804A (en) * 1990-10-16 1993-05-18 Oki Electric Industry, Co., Ltd. Method for dry etching
US5240554A (en) * 1991-01-22 1993-08-31 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5217570A (en) * 1991-01-31 1993-06-08 Sony Corporation Dry etching method
US5204280A (en) * 1992-04-09 1993-04-20 International Business Machines Corporation Process for fabricating multiple pillars inside a dram trench for increased capacitor surface
US5264076A (en) * 1992-12-17 1993-11-23 At&T Bell Laboratories Integrated circuit process using a "hard mask"

Also Published As

Publication number Publication date
JPH07258868A (ja) 1995-10-09
JP3550195B2 (ja) 2004-08-04
US5439847A (en) 1995-08-08
EP0652588B1 (de) 2001-01-24
KR100330438B1 (ko) 2002-11-27
EP0652588A3 (de) 1997-02-19
EP0652588A2 (de) 1995-05-10
KR950015610A (ko) 1995-06-17

Similar Documents

Publication Publication Date Title
DE69119871D1 (de) Verfahren zum Ätzen von Schichten mit vorgegebener Tiefe in integrierten Schaltungen
DE69323995D1 (de) Verfahren zum Abstimmen von elektronischen Antwortgeräten
DE69311432D1 (de) Schnittstelle zur Kopplung von elektronischen Schaltungen
DE3582556D1 (de) Verfahren zum herstellen von kontakten fuer integrierte schaltungen.
DE69301393D1 (de) Fassung zum testen von integrierten schaltkreisen
DE69421658D1 (de) Auslegungsmethode für mehrlagige gedruckte Schaltung
DE69430457D1 (de) Verfahren zum teilweisen Sägen von intergrierter Schaltkreise
DE69634952D1 (de) Verfahren zur verhinderung des eindringens in elektronische schaltungen
DE69317696D1 (de) Polyimid-Verfahren zum Schutz integrierter Schaltungen
DE68918982D1 (de) Verfahren zur Trennung integrierter Schaltkreise auf einem Substrat.
DE69030123D1 (de) Induktive Strukturen für halbleitende integrierte Schaltungen
DE3576900D1 (de) Verfahren zum herstellen von gedruckten schaltungen.
DE69738556D1 (de) Interaktiver cad-apparat zum entwerfen des zusammenbaus von logischen schaltungen
DE69306178D1 (de) Ablatives Verfahren für die Leiterplattentechnologie
DE69724192D1 (de) Verfahren zum Ätzen von Polyzidstrukturen
DE69528084D1 (de) Verfahren zum Entwurf einer integrierten Halbleiter-Schaltung
DE69122992D1 (de) Verfahren zum Herstellen elektrischer Kontakte an Gatestrukturen auf integrierten Schaltungen
DE3579977D1 (de) Methode zum entwurf logisch integrierter schaltungen.
DE69030223D1 (de) Gestapeltes Mehrschichtsubstrat zum Montieren integrierter Schaltungen
DE68921666D1 (de) Anordnung zum Löten von gedruckten Schaltungen.
DE58906591D1 (de) Schaltungsanordnung zum Schutz elektronischer Schaltungen vor Überspannung.
DE69426618D1 (de) Verfahren zum Ätzen von leitenden Schichten auf integrierten Schaltungen
DE3483455D1 (de) Verfahren zur selbstheilung von hochintegrierten schaltungen und selbstheilende hochintegrierte schaltung.
DE68907101D1 (de) Elektrobeschichtungsverfahren fuer photolacke auf gedruckten schaltungen.
DE69430035D1 (de) CMOS-Schaltung zum Ausführen von bollescher Funktionen

Legal Events

Date Code Title Description
8332 No legal effect for de