DE69419788T2 - DRAM-Speicher-Anordnung mit einem direkt an dem Ausgangdatenstift messbaren Selbstauffrischungszeitzyklus - Google Patents

DRAM-Speicher-Anordnung mit einem direkt an dem Ausgangdatenstift messbaren Selbstauffrischungszeitzyklus

Info

Publication number
DE69419788T2
DE69419788T2 DE69419788T DE69419788T DE69419788T2 DE 69419788 T2 DE69419788 T2 DE 69419788T2 DE 69419788 T DE69419788 T DE 69419788T DE 69419788 T DE69419788 T DE 69419788T DE 69419788 T2 DE69419788 T2 DE 69419788T2
Authority
DE
Germany
Prior art keywords
self
output data
time cycle
measured directly
dram memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69419788T
Other languages
English (en)
Other versions
DE69419788D1 (de
Inventor
Kenichi Sakakibara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69419788D1 publication Critical patent/DE69419788D1/de
Publication of DE69419788T2 publication Critical patent/DE69419788T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69419788T 1993-02-10 1994-02-07 DRAM-Speicher-Anordnung mit einem direkt an dem Ausgangdatenstift messbaren Selbstauffrischungszeitzyklus Expired - Lifetime DE69419788T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5045906A JP3001342B2 (ja) 1993-02-10 1993-02-10 記憶装置

Publications (2)

Publication Number Publication Date
DE69419788D1 DE69419788D1 (de) 1999-09-09
DE69419788T2 true DE69419788T2 (de) 2000-03-02

Family

ID=12732296

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69419788T Expired - Lifetime DE69419788T2 (de) 1993-02-10 1994-02-07 DRAM-Speicher-Anordnung mit einem direkt an dem Ausgangdatenstift messbaren Selbstauffrischungszeitzyklus

Country Status (5)

Country Link
US (1) US5418754A (de)
EP (1) EP0610862B1 (de)
JP (1) JP3001342B2 (de)
KR (1) KR960003996B1 (de)
DE (1) DE69419788T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5513144A (en) * 1995-02-13 1996-04-30 Micron Technology, Inc. On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same
JP3260583B2 (ja) * 1995-04-04 2002-02-25 株式会社東芝 ダイナミック型半導体メモリおよびそのテスト方法
US5835436A (en) 1995-07-03 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Dynamic type semiconductor memory device capable of transferring data between array blocks at high speed
US5745914A (en) * 1996-02-09 1998-04-28 International Business Machines Corporation Technique for converting system signals from one address configuration to a different address configuration
US6392948B1 (en) 1996-08-29 2002-05-21 Micron Technology, Inc. Semiconductor device with self refresh test mode
JP4000206B2 (ja) * 1996-08-29 2007-10-31 富士通株式会社 半導体記憶装置
JP3862333B2 (ja) * 1996-12-10 2006-12-27 株式会社ルネサステクノロジ 半導体記憶装置
US5790560A (en) * 1996-12-13 1998-08-04 International Business Machines Corporation Apparatus and method for timing self-timed circuitry
US6005812A (en) 1998-02-27 1999-12-21 Micron Technology, Inc. Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing
KR100364128B1 (ko) * 1999-04-08 2002-12-11 주식회사 하이닉스반도체 셀프리프레쉬 발진주기 측정장치
KR100387720B1 (ko) 1999-06-29 2003-06-18 주식회사 하이닉스반도체 반도체 메모리 소자의 셀프 리프레쉬 장치 및 방법
US6453373B1 (en) * 1999-12-30 2002-09-17 Intel Corporation Method and apparatus for differential strobing
JP2001195897A (ja) 2000-01-17 2001-07-19 Mitsubishi Electric Corp 半導体記憶装置
JP2003203497A (ja) * 2002-01-08 2003-07-18 Mitsubishi Electric Corp 半導体記憶装置
KR100548566B1 (ko) * 2003-07-24 2006-02-02 주식회사 하이닉스반도체 메모리 장치의 셀프 리프레쉬 주기 측정 방법 및 그 장치
KR100653688B1 (ko) * 2004-04-29 2006-12-04 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 리프레쉬 방법, 및 이장치를 위한 메모리 시스템
JP5082727B2 (ja) * 2007-09-28 2012-11-28 ソニー株式会社 記憶制御装置、記憶制御方法およびコンピュータプログラム

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01124195A (ja) * 1987-11-09 1989-05-17 Sharp Corp セルフリフレッシュ方式
JPH02105389A (ja) * 1988-10-13 1990-04-17 Matsushita Electron Corp ダイナミック型記憶装置
JP2928263B2 (ja) * 1989-03-20 1999-08-03 株式会社日立製作所 半導体装置
JPH03254497A (ja) * 1990-03-05 1991-11-13 Mitsubishi Electric Corp マイクロコンピュータ
JPH0474379A (ja) * 1990-07-16 1992-03-09 Nec Ic Microcomput Syst Ltd メモリ集積回路
JPH04372790A (ja) * 1991-06-21 1992-12-25 Sharp Corp 半導体記憶装置
KR940008147B1 (ko) * 1991-11-25 1994-09-03 삼성전자 주식회사 저전력 데이타 리텐션 기능을 가지는 반도체 메모리장치
KR950009390B1 (ko) * 1992-04-22 1995-08-21 삼성전자주식회사 반도체 메모리장치의 리프레시 어드레스 테스트회로

Also Published As

Publication number Publication date
DE69419788D1 (de) 1999-09-09
JP3001342B2 (ja) 2000-01-24
EP0610862A3 (en) 1995-12-13
US5418754A (en) 1995-05-23
JPH06236682A (ja) 1994-08-23
EP0610862B1 (de) 1999-08-04
KR960003996B1 (ko) 1996-03-25
EP0610862A2 (de) 1994-08-17
KR940020416A (ko) 1994-09-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP