DE69418153D1 - Speicheranordnung und serielle/parallele Datenwandlerschaltung - Google Patents

Speicheranordnung und serielle/parallele Datenwandlerschaltung

Info

Publication number
DE69418153D1
DE69418153D1 DE69418153T DE69418153T DE69418153D1 DE 69418153 D1 DE69418153 D1 DE 69418153D1 DE 69418153 T DE69418153 T DE 69418153T DE 69418153 T DE69418153 T DE 69418153T DE 69418153 D1 DE69418153 D1 DE 69418153D1
Authority
DE
Germany
Prior art keywords
serial
converter circuit
parallel data
data converter
memory arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69418153T
Other languages
English (en)
Other versions
DE69418153T2 (de
Inventor
Haruki Toda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69418153D1 publication Critical patent/DE69418153D1/de
Publication of DE69418153T2 publication Critical patent/DE69418153T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69418153T 1993-11-29 1994-11-29 Speicheranordnung und serielle/parallele Datenwandlerschaltung Expired - Fee Related DE69418153T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29807493A JP3547466B2 (ja) 1993-11-29 1993-11-29 メモリ装置、シリアル‐パラレルデータ変換回路、メモリ装置にデータを書き込む方法、およびシリアル‐パラレルデータ変換方法

Publications (2)

Publication Number Publication Date
DE69418153D1 true DE69418153D1 (de) 1999-06-02
DE69418153T2 DE69418153T2 (de) 1999-09-23

Family

ID=17854816

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69418153T Expired - Fee Related DE69418153T2 (de) 1993-11-29 1994-11-29 Speicheranordnung und serielle/parallele Datenwandlerschaltung

Country Status (5)

Country Link
US (3) US5568428A (de)
EP (1) EP0655741B1 (de)
JP (1) JP3547466B2 (de)
KR (1) KR100235134B1 (de)
DE (1) DE69418153T2 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW389909B (en) 1995-09-13 2000-05-11 Toshiba Corp Nonvolatile semiconductor memory device and its usage
US6166979A (en) * 1995-09-13 2000-12-26 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method for using the same
US6035369A (en) 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
US5703810A (en) * 1995-12-15 1997-12-30 Silicon Graphics, Inc. DRAM for texture mapping
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US5872736A (en) * 1996-10-28 1999-02-16 Micron Technology, Inc. High speed input buffer
US5917758A (en) 1996-11-04 1999-06-29 Micron Technology, Inc. Adjustable output driver circuit
US5949254A (en) * 1996-11-26 1999-09-07 Micron Technology, Inc. Adjustable output driver circuit
US6115318A (en) 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
US5838177A (en) * 1997-01-06 1998-11-17 Micron Technology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5732036A (en) * 1997-02-14 1998-03-24 Micron Technology, Inc. Memory device communication line control
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US5956502A (en) * 1997-03-05 1999-09-21 Micron Technology, Inc. Method and circuit for producing high-speed counts
US5898638A (en) * 1997-03-11 1999-04-27 Micron Technology, Inc. Latching wordline driver for multi-bank memory
US5870347A (en) * 1997-03-11 1999-02-09 Micron Technology, Inc. Multi-bank memory input/output line selection
WO1998054727A2 (en) 1997-05-30 1998-12-03 Micron Technology, Inc. 256 Meg DYNAMIC RANDOM ACCESS MEMORY
US6014759A (en) 1997-06-13 2000-01-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6044429A (en) 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
EP1019912A2 (de) * 1997-10-10 2000-07-19 Rambus Incorporated Speichersystem mit pipeline
US5923594A (en) * 1998-02-17 1999-07-13 Micron Technology, Inc. Method and apparatus for coupling data from a memory device using a single ended read data path
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6055587A (en) * 1998-03-27 2000-04-25 Adaptec, Inc, Integrated circuit SCSI I/O cell having signal assertion edge triggered timed glitch filter that defines a strobe masking period to protect the contents of data latches
US6405280B1 (en) 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
JP4424770B2 (ja) * 1998-12-25 2010-03-03 株式会社ルネサステクノロジ 半導体記憶装置
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
JP3408479B2 (ja) * 1999-12-17 2003-05-19 日本電気株式会社 半導体記憶装置
JP2002109881A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体集積回路
US6501698B1 (en) * 2000-11-01 2002-12-31 Enhanced Memory Systems, Inc. Structure and method for hiding DRAM cycle time behind a burst access
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7349266B2 (en) * 2004-06-10 2008-03-25 Freescale Semiconductor, Inc. Memory device with a data hold latch
USD949667S1 (en) 2020-04-07 2022-04-26 Intelligent Designs 2000 Corp. Double loop swivel hook

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH069114B2 (ja) * 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
DE3605431A1 (de) * 1986-02-20 1987-08-27 Vdo Schindling Pruefbares elektronisches geraet und verfahren zum pruefen eines solchen geraets
US5018109A (en) * 1987-01-16 1991-05-21 Hitachi, Ltd. Memory including address registers for increasing access speed to the memory
US4821226A (en) * 1987-01-30 1989-04-11 Rca Licensing Corporation Dual port video memory system having a bit-serial address input port
US4817058A (en) * 1987-05-21 1989-03-28 Texas Instruments Incorporated Multiple input/output read/write memory having a multiple-cycle write mask
JPH01146187A (ja) * 1987-12-02 1989-06-08 Mitsubishi Electric Corp キヤッシュメモリ内蔵半導体記憶装置
JP2591010B2 (ja) * 1988-01-29 1997-03-19 日本電気株式会社 シリアルアクセスメモリ装置
DE69020384T2 (de) * 1989-02-27 1996-03-21 Nec Corp Integrierte Halbleiterspeicherschaltung mit Möglichkeit zum Maskieren des Schreibens im Speicher.
JPH07109703B2 (ja) * 1989-11-15 1995-11-22 株式会社東芝 半導体メモリ装置
DE4118804C2 (de) * 1990-06-08 1996-01-04 Toshiba Kawasaki Kk Serienzugriff-Speicheranordnung
JP3105319B2 (ja) * 1991-12-19 2000-10-30 株式会社 沖マイクロデザイン シリアルアクセスメモリ

Also Published As

Publication number Publication date
DE69418153T2 (de) 1999-09-23
KR950015373A (ko) 1995-06-16
JP3547466B2 (ja) 2004-07-28
EP0655741B1 (de) 1999-04-28
EP0655741A2 (de) 1995-05-31
KR100235134B1 (ko) 1999-12-15
US5796660A (en) 1998-08-18
JPH07153254A (ja) 1995-06-16
EP0655741A3 (de) 1996-12-18
US5568428A (en) 1996-10-22
US5644537A (en) 1997-07-01

Similar Documents

Publication Publication Date Title
DE69418153T2 (de) Speicheranordnung und serielle/parallele Datenwandlerschaltung
DE59401033D1 (de) Kühlmittelkreislauf
DE69434615D1 (de) Leistungsschaltung
DE69230248T2 (de) Modulationsverfahren und Schaltungsanordnung dafür
DE69317944D1 (de) Integrierte Speicherschaltung
DE59407727D1 (de) Baugruppenträger
DE69427339D1 (de) Begrenzungsschaltung
DE69421956T2 (de) Spannung-Strom-Wandlerschaltung
DE69322630D1 (de) Integriertes Schaltungsbauelement hoher Dichte
DE69410836T2 (de) Schaltkreis
DE69428667D1 (de) Parallel-zur-seriell-Datenumsetzungsschaltung
DE69324750D1 (de) Serien-/Parallel-Datenumsetzer
DE69322749D1 (de) Datenleseverfahren und festwertspeicherschaltung
DE69428421T2 (de) Nicht-reziprokes schaltungselement
KR930007252U (ko) 직병렬 데이타 컨버터회로
DE69423202T2 (de) Bildspeicherschaltung und Bildspeichersystem
DE59307800D1 (de) Wandlerschaltung
DE9314399U1 (de) Signalgesteuerter Schaltungsanordnung
DE9309825U1 (de) Schaltungsanordnung
DE69313257D1 (de) Schaltung
DE9314174U1 (de) Baugruppenträger
KR950016012U (ko) 컨버터 회로
KR960018634U (ko) 데이타 직, 병렬 변환회로
KR950023825U (ko) 메모리 공유 회로
KR950012369U (ko) 메모리선택회로

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee