DE69321864D1 - Verfahren und Vorrichtung zur Verkapselung von dreidimensionalen Halbleiterplättchen - Google Patents

Verfahren und Vorrichtung zur Verkapselung von dreidimensionalen Halbleiterplättchen

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Publication number
DE69321864D1
DE69321864D1 DE69321864T DE69321864T DE69321864D1 DE 69321864 D1 DE69321864 D1 DE 69321864D1 DE 69321864 T DE69321864 T DE 69321864T DE 69321864 T DE69321864 T DE 69321864T DE 69321864 D1 DE69321864 D1 DE 69321864D1
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DE
Germany
Prior art keywords
encapsulating
semiconductor wafers
dimensional semiconductor
dimensional
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69321864T
Other languages
English (en)
Other versions
DE69321864T2 (de
Inventor
Christian Val
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of DE69321864D1 publication Critical patent/DE69321864D1/de
Application granted granted Critical
Publication of DE69321864T2 publication Critical patent/DE69321864T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
DE69321864T 1992-03-10 1993-03-05 Verfahren und Vorrichtung zur Verkapselung von dreidimensionalen Halbleiterplättchen Expired - Lifetime DE69321864T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9202846A FR2688629A1 (fr) 1992-03-10 1992-03-10 Procede et dispositif d'encapsulation en trois dimensions de pastilles semi-conductrices.

Publications (2)

Publication Number Publication Date
DE69321864D1 true DE69321864D1 (de) 1998-12-10
DE69321864T2 DE69321864T2 (de) 1999-04-01

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DE69321864T Expired - Lifetime DE69321864T2 (de) 1992-03-10 1993-03-05 Verfahren und Vorrichtung zur Verkapselung von dreidimensionalen Halbleiterplättchen

Country Status (5)

Country Link
US (1) US5400218A (de)
EP (1) EP0565391B1 (de)
JP (1) JP3326858B2 (de)
DE (1) DE69321864T2 (de)
FR (1) FR2688629A1 (de)

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FR2709020B1 (fr) * 1993-08-13 1995-09-08 Thomson Csf Procédé d'interconnexion de pastilles semi-conductrices en trois dimensions, et composant en résultant.
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FR2756133B1 (fr) * 1996-11-21 1999-06-11 Alsthom Cge Alcatel Assemblage de modules electroniques multi-niveaux
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US5903057A (en) * 1997-11-07 1999-05-11 Intel Corporation Semiconductor device that compensates for package induced delay
JP3304921B2 (ja) * 1999-06-18 2002-07-22 日本電気株式会社 半導体記憶装置
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US5400218A (en) 1995-03-21
FR2688629A1 (fr) 1993-09-17
DE69321864T2 (de) 1999-04-01
JPH06132471A (ja) 1994-05-13
EP0565391A1 (de) 1993-10-13
JP3326858B2 (ja) 2002-09-24
EP0565391B1 (de) 1998-11-04

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