DE69015511D1 - Verfahren und Vorrichtung zum Verbinden von Halbleitersubstraten. - Google Patents

Verfahren und Vorrichtung zum Verbinden von Halbleitersubstraten.

Info

Publication number
DE69015511D1
DE69015511D1 DE69015511T DE69015511T DE69015511D1 DE 69015511 D1 DE69015511 D1 DE 69015511D1 DE 69015511 T DE69015511 T DE 69015511T DE 69015511 T DE69015511 T DE 69015511T DE 69015511 D1 DE69015511 D1 DE 69015511D1
Authority
DE
Germany
Prior art keywords
semiconductor substrates
connecting semiconductor
substrates
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69015511T
Other languages
English (en)
Other versions
DE69015511T2 (de
Inventor
Tadahide Hoshi
Kiyoshi Yoshikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69015511D1 publication Critical patent/DE69015511D1/de
Application granted granted Critical
Publication of DE69015511T2 publication Critical patent/DE69015511T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE69015511T 1989-08-28 1990-08-28 Verfahren und Vorrichtung zum Verbinden von Halbleitersubstraten. Expired - Lifetime DE69015511T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1221337A JPH0744135B2 (ja) 1989-08-28 1989-08-28 半導体基板の接着方法及び接着装置

Publications (2)

Publication Number Publication Date
DE69015511D1 true DE69015511D1 (de) 1995-02-09
DE69015511T2 DE69015511T2 (de) 1995-05-24

Family

ID=16765225

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015511T Expired - Lifetime DE69015511T2 (de) 1989-08-28 1990-08-28 Verfahren und Vorrichtung zum Verbinden von Halbleitersubstraten.

Country Status (5)

Country Link
US (1) US5129827A (de)
EP (1) EP0415340B1 (de)
JP (1) JPH0744135B2 (de)
KR (1) KR940009993B1 (de)
DE (1) DE69015511T2 (de)

Families Citing this family (47)

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USRE36890E (en) * 1990-07-31 2000-10-03 Motorola, Inc. Gradient chuck method for wafer bonding employing a convex pressure
KR100289348B1 (ko) * 1992-05-25 2001-12-28 이데이 노부유끼 절연기판실리콘반도체장치와그제조방법
US5300175A (en) * 1993-01-04 1994-04-05 Motorola, Inc. Method for mounting a wafer to a submount
JP3321882B2 (ja) * 1993-02-28 2002-09-09 ソニー株式会社 基板はり合わせ方法
JP2723787B2 (ja) * 1993-08-20 1998-03-09 信越半導体株式会社 結合型基板の製造方法
US5401670A (en) * 1993-09-15 1995-03-28 Yen; Yung-Chau Technique to manufacture a SOI wafer and its applications in integrated circuits manufacturing
US6116316A (en) * 1996-05-13 2000-09-12 Toolex Alpha Ab Device for bending a flat, round disc element
JP3720515B2 (ja) * 1997-03-13 2005-11-30 キヤノン株式会社 基板処理装置及びその方法並びに基板の製造方法
JPH1174164A (ja) 1997-08-27 1999-03-16 Canon Inc 基板処理装置、基板支持装置及び基板処理方法並びに基板の製造方法
US6106657A (en) * 1998-05-19 2000-08-22 First Light Technology, Inc. System and method for dispensing a resin between substrates of a bonded storage disk
FR2802340B1 (fr) * 1999-12-13 2003-09-05 Commissariat Energie Atomique Structure comportant des cellules photovoltaiques et procede de realisation
DE10030431A1 (de) * 2000-06-21 2002-01-10 Karl Suess Kg Praez Sgeraete F Verfahren und Vorrichtung zum Reinigen und/oder Bonden von Substraten
KR20020032042A (ko) * 2000-10-25 2002-05-03 최우범 기판 접합장치의 조절형 원뿔탐침 스페이서
GB2375733B (en) * 2001-01-15 2004-11-03 Lintec Corp Laminating apparatus and laminating method
US6635941B2 (en) * 2001-03-21 2003-10-21 Canon Kabushiki Kaisha Structure of semiconductor device with improved reliability
DE10140133A1 (de) * 2001-08-16 2003-03-13 Wacker Siltronic Halbleitermat Verfahren und Vorrichtung zum Herstellen einer klebenden Verbindung zwischen einer Halbleiterscheibe und einer Trägerplatte
TWI283906B (en) * 2001-12-21 2007-07-11 Esec Trading Sa Pick-up tool for mounting semiconductor chips
JP4233802B2 (ja) * 2002-04-26 2009-03-04 東レエンジニアリング株式会社 実装方法および実装装置
FR2848337B1 (fr) * 2002-12-09 2005-09-09 Commissariat Energie Atomique Procede de realisation d'une structure complexe par assemblage de structures contraintes
JP4777681B2 (ja) * 2005-04-08 2011-09-21 Ｏｋｉセミコンダクタ株式会社 陽極接合装置、陽極接合方法及び加速度センサの製造方法
JP4671841B2 (ja) * 2005-11-09 2011-04-20 パナソニック株式会社 対象物間の脱ガス方法および脱ガス装置
JP4958147B2 (ja) * 2006-10-18 2012-06-20 Ｈｏｙａ株式会社 露光用反射型マスクブランク及び露光用反射型マスク、多層反射膜付き基板、並びに半導体装置の製造方法
US8037918B2 (en) * 2006-12-04 2011-10-18 Stats Chippac, Inc. Pick-up heads and systems for die bonding and related applications
JP5303883B2 (ja) * 2007-09-04 2013-10-02 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造装置及び製造方法
KR101562021B1 (ko) * 2009-08-11 2015-10-20 삼성전자주식회사 반도체 칩 부착 장치 및 반도체 칩 부착 방법
US8334191B2 (en) * 2009-12-11 2012-12-18 Twin Creeks Technology, Inc. Two-chamber system and method for serial bonding and exfoliation of multiple workpieces
CN102947923B (zh) * 2010-06-02 2015-11-25 库卡系统有限责任公司 制造装置和方法
JP2012004296A (ja) * 2010-06-16 2012-01-05 Sumitomo Electric Ind Ltd 複合基板の製造方法および複合基板
FR2965974B1 (fr) 2010-10-12 2013-11-29 Soitec Silicon On Insulator Procédé de collage moléculaire de substrats en silicium et en verre
TWI564982B (zh) * 2011-04-26 2017-01-01 尼康股份有限公司 A substrate holding device, a substrate bonding device, a substrate holding method, a substrate bonding method, a laminated semiconductor device, and a laminated substrate
KR102350216B1 (ko) * 2011-08-12 2022-01-11 에베 그룹 에. 탈너 게엠베하 기판의 접합을 위한 장치 및 방법
JP2013165219A (ja) * 2012-02-13 2013-08-22 Toshiba Corp ダイボンディング装置、コレット、および、ダイボンディング方法
US20130312907A1 (en) * 2012-05-23 2013-11-28 Lg Display Co., Ltd. Substrate-bonding apparatus for display device and method for manufacturing bonded substrate
KR101990854B1 (ko) * 2012-05-23 2019-06-19 엘지디스플레이 주식회사 디스플레이장치용 합착장치 및 합착기판 제조방법
KR101932124B1 (ko) * 2013-04-03 2018-12-26 삼성디스플레이 주식회사 지그 조립체, 라미네이트 장치 및 이를 이용한 라미네이트 방법
CN109449082B (zh) * 2013-05-29 2023-06-02 Ev 集团 E·索尔纳有限责任公司 用以接合衬底的装置及方法
US9837291B2 (en) * 2014-01-24 2017-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer processing method and apparatus
US9576827B2 (en) 2014-06-06 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for wafer level bonding
JP6177739B2 (ja) * 2014-08-07 2017-08-09 東京エレクトロン株式会社 接合装置、接合システム、接合方法、プログラム及びコンピュータ記憶媒体
US10446728B2 (en) * 2014-10-31 2019-10-15 eLux, Inc. Pick-and remove system and method for emissive display repair
US9490158B2 (en) 2015-01-08 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Bond chuck, methods of bonding, and tool including bond chuck
JP6407803B2 (ja) * 2015-06-16 2018-10-17 東京エレクトロン株式会社 接合装置、接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP6616181B2 (ja) * 2015-12-25 2019-12-04 東京エレクトロン株式会社 接合装置
JP6685154B2 (ja) * 2016-03-14 2020-04-22 東京エレクトロン株式会社 接合装置および接合方法
US10991609B2 (en) * 2016-08-12 2021-04-27 Ev Group E. Thallner Gmbh Method and substrate holder for the controlled bonding of substrates
KR20200133634A (ko) 2019-05-20 2020-11-30 삼성전자주식회사 기판 본딩 장치 및 이를 이용한 반도체 소자 제조 방법
EP4055624B1 (de) * 2019-11-08 2023-09-27 EV Group E. Thallner GmbH Vorrichtung und verfahren zum verbinden von substraten

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3417459A (en) * 1965-05-06 1968-12-24 Mallory & Co Inc P R Bonding electrically conductive metals to insulators
JPH0691006B2 (ja) * 1984-05-10 1994-11-14 株式会社東芝 半導体ウエハの接合方法
US4752180A (en) * 1985-02-14 1988-06-21 Kabushiki Kaisha Toshiba Method and apparatus for handling semiconductor wafers
JPS62158905A (ja) * 1985-12-28 1987-07-14 Tokyo Gas Co Ltd コ−クス炉に於ける排ガス再循環切換燃焼方法
DE3670178D1 (de) * 1986-08-13 1990-05-10 Toshiba Kawasaki Kk Apparat zum zusammenfuegen von halbleiterscheiben.
US4830984A (en) * 1987-08-19 1989-05-16 Texas Instruments Incorporated Method for heteroepitaxial growth using tensioning layer on rear substrate surface
JPH0256918A (ja) * 1988-05-24 1990-02-26 Nippon Denso Co Ltd 半導体ウェハの直接接合方法
US4939101A (en) * 1988-09-06 1990-07-03 General Electric Company Method of making direct bonded wafers having a void free interface

Also Published As

Publication number Publication date
JPH0384919A (ja) 1991-04-10
KR910005382A (ko) 1991-03-30
DE69015511T2 (de) 1995-05-24
US5129827A (en) 1992-07-14
EP0415340A1 (de) 1991-03-06
JPH0744135B2 (ja) 1995-05-15
KR940009993B1 (en) 1994-10-19
EP0415340B1 (de) 1994-12-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)