DE69033452D1 - Vorrichtung und Verfahren zum Behandeln von Substraten - Google Patents

Vorrichtung und Verfahren zum Behandeln von Substraten

Info

Publication number
DE69033452D1
DE69033452D1 DE69033452T DE69033452T DE69033452D1 DE 69033452 D1 DE69033452 D1 DE 69033452D1 DE 69033452 T DE69033452 T DE 69033452T DE 69033452 T DE69033452 T DE 69033452T DE 69033452 D1 DE69033452 D1 DE 69033452D1
Authority
DE
Germany
Prior art keywords
treating substrates
substrates
treating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69033452T
Other languages
English (en)
Other versions
DE69033452T2 (de
Inventor
Izumi Arai
Yoshifumi Tahara
Yoshio Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of DE69033452D1 publication Critical patent/DE69033452D1/de
Application granted granted Critical
Publication of DE69033452T2 publication Critical patent/DE69033452T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
DE69033452T 1989-09-08 1990-09-07 Vorrichtung und Verfahren zum Behandeln von Substraten Expired - Fee Related DE69033452T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23334189 1989-09-08

Publications (2)

Publication Number Publication Date
DE69033452D1 true DE69033452D1 (de) 2000-03-16
DE69033452T2 DE69033452T2 (de) 2000-06-29

Family

ID=16953633

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69033452T Expired - Fee Related DE69033452T2 (de) 1989-09-08 1990-09-07 Vorrichtung und Verfahren zum Behandeln von Substraten

Country Status (4)

Country Link
US (1) US5164034A (de)
EP (1) EP0416646B1 (de)
KR (1) KR0154329B1 (de)
DE (1) DE69033452T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2888258B2 (ja) * 1990-11-30 1999-05-10 東京エレクトロン株式会社 基板処理装置および基板処理方法
JP3030160B2 (ja) * 1992-04-28 2000-04-10 東京エレクトロン株式会社 真空処理装置
JPH06188229A (ja) * 1992-12-16 1994-07-08 Tokyo Electron Yamanashi Kk エッチングの後処理方法
US5624582A (en) * 1993-01-21 1997-04-29 Vlsi Technology, Inc. Optimization of dry etching through the control of helium backside pressure
US5342476A (en) * 1993-01-21 1994-08-30 Vlsi Technology, Inc. Reduction of polycide residues through helium backside pressure control during dry etching
EP0938134A3 (de) * 1993-05-20 2000-01-19 Hitachi, Ltd. Verfahren zum Plasma-Äzen
JP3328416B2 (ja) * 1994-03-18 2002-09-24 富士通株式会社 半導体装置の製造方法と製造装置
JP2994553B2 (ja) * 1994-04-08 1999-12-27 大日本スクリーン製造株式会社 基板処理装置
JP3529849B2 (ja) * 1994-05-23 2004-05-24 富士通株式会社 半導体装置の製造方法
US5745364A (en) * 1994-12-28 1998-04-28 Nec Corporation Method of producing semiconductor wafer
JP2996159B2 (ja) * 1995-10-26 1999-12-27 ヤマハ株式会社 ドライエッチング方法
US5795831A (en) * 1996-10-16 1998-08-18 Ulvac Technologies, Inc. Cold processes for cleaning and stripping photoresist from surfaces of semiconductor wafers
JP4705816B2 (ja) 2005-07-27 2011-06-22 株式会社日立ハイテクノロジーズ プラズマ処理装置
JP2008263093A (ja) * 2007-04-13 2008-10-30 Tokyo Electron Ltd エッチング方法、エッチングシステムおよびエッチング装置
JP5280784B2 (ja) * 2007-11-21 2013-09-04 日本碍子株式会社 成膜装置

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1499857A (en) * 1975-09-18 1978-02-01 Standard Telephones Cables Ltd Glow discharge etching
JPS5951561B2 (ja) * 1978-09-01 1984-12-14 株式会社興人 セルロ−スエ−テルの製造方法
JPS5598232A (en) * 1979-01-22 1980-07-26 Agency Of Ind Science & Technol Internal treatment of plastic tube member
CA1159012A (en) * 1980-05-02 1983-12-20 Seitaro Matsuo Plasma deposition apparatus
JPS5799743A (en) * 1980-12-11 1982-06-21 Matsushita Electric Ind Co Ltd Apparatus and method of plasma etching
US4341582A (en) * 1980-12-22 1982-07-27 The Perkin-Elmer Corporation Load-lock vacuum chamber
JPS6037129A (ja) * 1983-08-10 1985-02-26 Hitachi Ltd 半導体製造装置
JPS6052013A (ja) * 1983-08-31 1985-03-23 Mitsubishi Electric Corp 光ｃｖｄ装置
US4555303A (en) * 1984-10-02 1985-11-26 Motorola, Inc. Oxidation of material in high pressure oxygen plasma
US4657618A (en) * 1984-10-22 1987-04-14 Texas Instruments Incorporated Powered load lock electrode/substrate assembly including robot arm, optimized for plasma process uniformity and rate
US4891087A (en) * 1984-10-22 1990-01-02 Texas Instruments Incorporated Isolation substrate ring for plasma reactor
JPS61222534A (ja) * 1985-03-28 1986-10-03 Anelva Corp 表面処理方法および装置
CA1247757A (en) * 1985-05-03 1988-12-28 The Australian National University Method and apparatus for producing large volume magnetoplasmas
US4689112A (en) * 1985-05-17 1987-08-25 Emergent Technologies Corporation Method and apparatus for dry processing of substrates
JP2635021B2 (ja) * 1985-09-26 1997-07-30 宣夫 御子柴 堆積膜形成法及びこれに用いる装置
US4842680A (en) * 1985-10-24 1989-06-27 Texas Instruments Incorporated Advanced vacuum processor
US4715921A (en) * 1986-10-24 1987-12-29 General Signal Corporation Quad processor
US4885047A (en) * 1986-08-11 1989-12-05 Fusion Systems Corporation Apparatus for photoresist stripping
JPS63116428A (ja) * 1986-11-05 1988-05-20 Hitachi Ltd ドライエツチング方法
JPH0834205B2 (ja) * 1986-11-21 1996-03-29 株式会社東芝 ドライエツチング装置
US4956043A (en) * 1987-05-25 1990-09-11 Hitachi, Ltd. Dry etching apparatus
JP2669523B2 (ja) * 1987-05-29 1997-10-29 東京エレクトロン株式会社 基板処理装置
US4818326A (en) * 1987-07-16 1989-04-04 Texas Instruments Incorporated Processing apparatus
KR970003885B1 (ko) * 1987-12-25 1997-03-22 도오교오 에레구토론 가부시끼 가이샤 에칭 방법 및 그 장치
US4908095A (en) * 1988-05-02 1990-03-13 Tokyo Electron Limited Etching device, and etching method
US5002794A (en) * 1989-08-31 1991-03-26 The Board Of Regents Of The University Of Washington Method of controlling the chemical structure of polymeric films by plasma

Also Published As

Publication number Publication date
EP0416646A3 (en) 1991-08-28
KR910007100A (ko) 1991-04-30
KR0154329B1 (ko) 1998-12-01
US5164034A (en) 1992-11-17
DE69033452T2 (de) 2000-06-29
EP0416646A2 (de) 1991-03-13
EP0416646B1 (de) 2000-02-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee