DE69211218D1 - Dünnfilm Feldeffektanordnung mit einer LDD-Struktur und Verfahren zur Herstellung - Google Patents

Dünnfilm Feldeffektanordnung mit einer LDD-Struktur und Verfahren zur Herstellung

Info

Publication number
DE69211218D1
DE69211218D1 DE69211218T DE69211218T DE69211218D1 DE 69211218 D1 DE69211218 D1 DE 69211218D1 DE 69211218 T DE69211218 T DE 69211218T DE 69211218 T DE69211218 T DE 69211218T DE 69211218 D1 DE69211218 D1 DE 69211218D1
Authority
DE
Germany
Prior art keywords
production
thin film
field effect
ldd structure
film field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69211218T
Other languages
English (en)
Other versions
DE69211218T2 (de
Inventor
Motoi Ashida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE69211218D1 publication Critical patent/DE69211218D1/de
Application granted granted Critical
Publication of DE69211218T2 publication Critical patent/DE69211218T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
DE69211218T 1991-04-23 1992-03-27 Dünnfilm Feldeffektanordnung mit einer LDD-Struktur und Verfahren zur Herstellung Expired - Fee Related DE69211218T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3091819A JPH04322469A (ja) 1991-04-23 1991-04-23 薄膜電界効果素子およびその製造方法

Publications (2)

Publication Number Publication Date
DE69211218D1 true DE69211218D1 (de) 1996-07-11
DE69211218T2 DE69211218T2 (de) 1996-11-07

Family

ID=14037242

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69211218T Expired - Fee Related DE69211218T2 (de) 1991-04-23 1992-03-27 Dünnfilm Feldeffektanordnung mit einer LDD-Struktur und Verfahren zur Herstellung

Country Status (5)

Country Link
US (1) US5262655A (de)
EP (1) EP0510380B1 (de)
JP (1) JPH04322469A (de)
KR (1) KR950003941B1 (de)
DE (1) DE69211218T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801396A (en) * 1989-01-18 1998-09-01 Stmicroelectronics, Inc. Inverted field-effect device with polycrystalline silicon/germanium channel
US5770892A (en) * 1989-01-18 1998-06-23 Sgs-Thomson Microelectronics, Inc. Field effect device with polycrystalline silicon channel
EP0565231A3 (en) * 1992-03-31 1996-11-20 Sgs Thomson Microelectronics Method of fabricating a polysilicon thin film transistor
US5411909A (en) * 1993-02-22 1995-05-02 Micron Technology, Inc. Method of forming a planar thin film transistor
US5373170A (en) * 1993-03-15 1994-12-13 Motorola Inc. Semiconductor memory device having a compact symmetrical layout
KR960012583B1 (en) * 1993-06-21 1996-09-23 Lg Semicon Co Ltd Tft (thin film transistor )and the method of manufacturing the same
JPH07131030A (ja) * 1993-11-05 1995-05-19 Sony Corp 表示用薄膜半導体装置及びその製造方法
US20040178446A1 (en) * 1994-02-09 2004-09-16 Ravishankar Sundaresan Method of forming asymmetrical polysilicon thin film transistor
US5488579A (en) * 1994-04-29 1996-01-30 Motorola Inc. Three-dimensionally integrated nonvolatile SRAM cell and process
US5573964A (en) * 1995-11-17 1996-11-12 International Business Machines Corporation Method of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer
JPH09153624A (ja) * 1995-11-30 1997-06-10 Sony Corp 半導体装置
US5808362A (en) * 1996-02-29 1998-09-15 Motorola, Inc. Interconnect structure and method of forming
US5602047A (en) * 1996-06-13 1997-02-11 Industrial Technology Research Institute Process for polysilicon thin film transistors using backside irradiation and plasma doping
US5773331A (en) * 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
US5953596A (en) * 1996-12-19 1999-09-14 Micron Technology, Inc. Methods of forming thin film transistors
KR100399291B1 (ko) * 1997-01-27 2004-01-24 가부시키가이샤 아드반스트 디스프레이 반도체 박막트랜지스터, 그 제조방법, 반도체 박막트랜지스터어레이 기판 및 해당 반도체 박막트랜지스터어레이 기판을 사용한 액정표시장치
US6140684A (en) * 1997-06-24 2000-10-31 Stmicroelectronic, Inc. SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers
US6174756B1 (en) * 1997-09-30 2001-01-16 Siemens Aktiengesellschaft Spacers to block deep junction implants and silicide formation in integrated circuits
KR100298438B1 (ko) 1998-01-26 2001-08-07 김영환 박막트랜지스터및이의제조방법
US6259131B1 (en) 1998-05-27 2001-07-10 Taiwan Semiconductor Manufacturing Company Poly tip and self aligned source for split-gate flash cell
US6117733A (en) * 1998-05-27 2000-09-12 Taiwan Semiconductor Manufacturing Company Poly tip formation and self-align source process for split-gate flash cell
KR100569716B1 (ko) * 1998-08-21 2006-08-11 삼성전자주식회사 액정 표시 장치의 박막 트랜지스터 구조
US6309928B1 (en) 1998-12-10 2001-10-30 Taiwan Semiconductor Manufacturing Company Split-gate flash cell
US6281552B1 (en) 1999-03-23 2001-08-28 Semiconductor Energy Laboratory Co., Ltd. Thin film transistors having ldd regions
US8822295B2 (en) * 2012-04-03 2014-09-02 International Business Machines Corporation Low extension dose implants in SRAM fabrication
CN104779300B (zh) * 2015-04-16 2016-05-25 京东方科技集团股份有限公司 一种多晶硅薄膜晶体管及其制作方法和显示装置
CN106992143B (zh) * 2016-01-21 2019-12-17 中芯国际集成电路制造(上海)有限公司 一种半导体器件以及制备方法、电子装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4502202A (en) * 1983-06-17 1985-03-05 Texas Instruments Incorporated Method for fabricating overlaid device in stacked CMOS
JPS60173875A (ja) * 1984-02-20 1985-09-07 Toshiba Corp 半導体装置の製造方法
US4628589A (en) * 1984-09-28 1986-12-16 Texas Instruments Incorporated Method for fabricating stacked CMOS structures
JPS6362272A (ja) * 1986-09-02 1988-03-18 Seiko Instr & Electronics Ltd 半導体装置の製造方法
JPS63260162A (ja) * 1987-04-17 1988-10-27 Nec Corp 積層型cmos半導体装置
JPH0714009B2 (ja) * 1987-10-15 1995-02-15 日本電気株式会社 Mos型半導体記憶回路装置
US5115288A (en) * 1990-06-28 1992-05-19 National Semiconductor Corporation Split-gate EPROM cell using polysilicon spacers
JPH1179367A (ja) * 1997-09-17 1999-03-23 Nkk Corp 廃棄瓶整列装置および廃棄瓶仕分装置

Also Published As

Publication number Publication date
JPH04322469A (ja) 1992-11-12
US5262655A (en) 1993-11-16
DE69211218T2 (de) 1996-11-07
KR950003941B1 (ko) 1995-04-21
EP0510380A3 (en) 1993-02-24
EP0510380B1 (de) 1996-06-05
EP0510380A2 (de) 1992-10-28
KR920020755A (ko) 1992-11-21

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee