DE69127527T2 - Speicheranordnung - Google Patents

Speicheranordnung

Info

Publication number
DE69127527T2
DE69127527T2 DE69127527T DE69127527T DE69127527T2 DE 69127527 T2 DE69127527 T2 DE 69127527T2 DE 69127527 T DE69127527 T DE 69127527T DE 69127527 T DE69127527 T DE 69127527T DE 69127527 T2 DE69127527 T2 DE 69127527T2
Authority
DE
Germany
Prior art keywords
memory cell
data
cell array
shift register
data bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127527T
Other languages
German (de)
English (en)
Other versions
DE69127527D1 (de
Inventor
Yasuharu Hoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Application granted granted Critical
Publication of DE69127527D1 publication Critical patent/DE69127527D1/de
Publication of DE69127527T2 publication Critical patent/DE69127527T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69127527T 1990-10-19 1991-10-17 Speicheranordnung Expired - Fee Related DE69127527T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2282826A JP2596208B2 (ja) 1990-10-19 1990-10-19 メモリ装置

Publications (2)

Publication Number Publication Date
DE69127527D1 DE69127527D1 (de) 1997-10-09
DE69127527T2 true DE69127527T2 (de) 1998-02-12

Family

ID=17657585

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127527T Expired - Fee Related DE69127527T2 (de) 1990-10-19 1991-10-17 Speicheranordnung

Country Status (5)

Country Link
US (1) US5343439A (enExample)
EP (1) EP0481494B1 (enExample)
JP (1) JP2596208B2 (enExample)
KR (1) KR0138751B1 (enExample)
DE (1) DE69127527T2 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940024597A (ko) * 1993-04-10 1994-11-18 김광호 듀얼포트 메모리장치의 시리얼데이타 입력장치.
JPH0713898A (ja) * 1993-06-29 1995-01-17 Mitsubishi Electric Corp 半導体集積回路装置
JPH07182893A (ja) * 1993-12-24 1995-07-21 Mitsubishi Electric Corp 半導体記憶装置
US5559753A (en) * 1995-01-25 1996-09-24 Dell Usa, L.P. Apparatus and method for preventing bus contention during power-up in a computer system with two or more DRAM banks
US5627786A (en) * 1995-02-10 1997-05-06 Micron Quantum Devices, Inc. Parallel processing redundancy scheme for faster access times and lower die area
US6108237A (en) * 1997-07-17 2000-08-22 Micron Technology, Inc. Fast-sensing amplifier for flash memory
US5682496A (en) 1995-02-10 1997-10-28 Micron Quantum Devices, Inc. Filtered serial event controlled command port for memory
US5610873A (en) * 1996-03-21 1997-03-11 National Science Council Of R.O.C. Address generator for generating a plurality of addresses to be used in zig-zag scanning of contents of memory array
US6172935B1 (en) 1997-04-25 2001-01-09 Micron Technology, Inc. Synchronous dynamic random access memory device
US6728799B1 (en) * 2000-01-13 2004-04-27 Hewlett-Packard Development Company, L.P. Hybrid data I/O for memory applications
US6993105B1 (en) 2000-05-09 2006-01-31 Cypress Semiconductor Corp. Linearized digital phase-locked loop
US6950484B1 (en) 2000-05-12 2005-09-27 Cypress Semiconductor Corp. Linearized digital phase-locked loop method
US6711226B1 (en) 2000-05-12 2004-03-23 Cypress Semiconductor Corp. Linearized digital phase-locked loop
US6535023B1 (en) 2000-05-12 2003-03-18 Cypress Semiconductor Corp. Linearized digital phase-locked loop method
US6417698B1 (en) * 2000-05-12 2002-07-09 Cypress Semiconductor Corp. Linearized digital phase-locked loop method
KR100598010B1 (ko) * 2004-08-06 2006-07-06 삼성전자주식회사 클럭 분배기, 클럭 분배기를 포함한 시스템, 클럭 분배방법 및 클럭 분배를 이용한 데이터 읽기 및 쓰기 방법
US7826581B1 (en) 2004-10-05 2010-11-02 Cypress Semiconductor Corporation Linearized digital phase-locked loop method for maintaining end of packet time linearity
WO2008124123A1 (en) * 2007-04-05 2008-10-16 Glenn Bradley J Stabilized elongate implantable vascular access device
US8717831B2 (en) 2012-04-30 2014-05-06 Hewlett-Packard Development Company, L.P. Memory circuit
US20150318054A1 (en) * 2012-12-11 2015-11-05 Hewlett-Packard Development Company, L.P. Data Operation in Shift Register Ring

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330852A (en) * 1979-11-23 1982-05-18 Texas Instruments Incorporated Semiconductor read/write memory array having serial access
JPH0760594B2 (ja) * 1987-06-25 1995-06-28 富士通株式会社 半導体記憶装置
US5195055A (en) * 1987-11-30 1993-03-16 Mitsubishi Denki Kabushiki Kaisha Serial data input circuit for the shifting-in of variable length data
JPH07107792B2 (ja) * 1988-01-19 1995-11-15 株式会社東芝 マルチポートメモリ
US4873671A (en) * 1988-01-28 1989-10-10 National Semiconductor Corporation Sequential read access of serial memories with a user defined starting address
JPH01224993A (ja) * 1988-03-04 1989-09-07 Nec Corp マルチポートメモリ
JPH0748316B2 (ja) * 1988-05-30 1995-05-24 日本電気株式会社 デュアルポートメモリ回路
US5084839A (en) * 1990-02-05 1992-01-28 Harris Corporation Variable length shift register

Also Published As

Publication number Publication date
EP0481494B1 (en) 1997-09-03
JP2596208B2 (ja) 1997-04-02
EP0481494A3 (enExample) 1994-12-14
KR0138751B1 (ko) 1998-06-15
JPH04157692A (ja) 1992-05-29
DE69127527D1 (de) 1997-10-09
US5343439A (en) 1994-08-30
KR920008750A (ko) 1992-05-28
EP0481494A2 (en) 1992-04-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee