DE69126514T2 - Serieller Speicher - Google Patents

Serieller Speicher

Info

Publication number
DE69126514T2
DE69126514T2 DE69126514T DE69126514T DE69126514T2 DE 69126514 T2 DE69126514 T2 DE 69126514T2 DE 69126514 T DE69126514 T DE 69126514T DE 69126514 T DE69126514 T DE 69126514T DE 69126514 T2 DE69126514 T2 DE 69126514T2
Authority
DE
Germany
Prior art keywords
memory
output
input
circuit
sequential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69126514T
Other languages
German (de)
English (en)
Other versions
DE69126514D1 (de
Inventor
Morris D Ward
Kenneth L Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69126514D1 publication Critical patent/DE69126514D1/de
Application granted granted Critical
Publication of DE69126514T2 publication Critical patent/DE69126514T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69126514T 1990-12-17 1991-12-17 Serieller Speicher Expired - Fee Related DE69126514T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US62827990A 1990-12-17 1990-12-17

Publications (2)

Publication Number Publication Date
DE69126514D1 DE69126514D1 (de) 1997-07-17
DE69126514T2 true DE69126514T2 (de) 1997-12-04

Family

ID=24518214

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69126514T Expired - Fee Related DE69126514T2 (de) 1990-12-17 1991-12-17 Serieller Speicher

Country Status (6)

Country Link
US (1) US5594700A (OSRAM)
EP (1) EP0495217B1 (OSRAM)
JP (1) JPH06131154A (OSRAM)
KR (1) KR100275182B1 (OSRAM)
DE (1) DE69126514T2 (OSRAM)
TW (1) TW198116B (OSRAM)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305281A (en) * 1992-08-06 1994-04-19 National Semiconductor Corporation Multiple array memory device with staggered read/write for high speed data access
US5838631A (en) * 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US5748539A (en) * 1997-03-05 1998-05-05 Sun Microsystems, Inc. Recursive multi-channel interface
US5933385A (en) * 1997-07-31 1999-08-03 Integrated Silicon Solution Inc. System and method for a flexible memory controller
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US6038185A (en) * 1998-05-12 2000-03-14 Atmel Corporation Method and apparatus for a serial access memory
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
JP4081963B2 (ja) * 2000-06-30 2008-04-30 セイコーエプソン株式会社 記憶装置および記憶装置に対するアクセス方法
US7392638B2 (en) * 2000-08-10 2008-07-01 Baxa Corporation Method, system, and apparatus for handling, labeling, filling, and capping syringes with improved cap
EP1313644B1 (en) * 2000-08-10 2007-12-19 Baxa Corporation Article for handling, labeling, filling, and capping syringes
US6745277B1 (en) * 2000-10-04 2004-06-01 Force10 Networks, Inc. Intelligent interleaving scheme for multibank memory
US6430099B1 (en) * 2001-05-11 2002-08-06 Broadcom Corporation Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation
KR100452640B1 (ko) * 2002-11-11 2004-10-14 한국전자통신연구원 데이터 패킷 수신 장치 및 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862419A (en) * 1983-11-10 1989-08-29 Advanced Micro Devices, Inc. High speed pointer based first-in-first-out memory
US4864543A (en) * 1987-04-30 1989-09-05 Texas Instruments Incorporated First-in, first-out memory with counter address pointers for generating multiple memory status flags
JPH0817029B2 (ja) * 1986-12-19 1996-02-21 富士通株式会社 半導体記憶装置
DE3786539T2 (de) * 1986-12-19 1993-10-28 Fujitsu Ltd Halbleiterspeicher mit Doppelzugriffseinrichtung zur Realisierung eines Lesebetriebs mit hoher Geschwindigkeit.
JP2764908B2 (ja) * 1988-02-04 1998-06-11 日本電気株式会社 カスケード・バッファ回路
JP2805761B2 (ja) * 1988-08-29 1998-09-30 日本電気株式会社 スタティックメモリ
US5027326A (en) * 1988-11-10 1991-06-25 Dallas Semiconductor Corporation Self-timed sequential access multiport memory
US4888741A (en) * 1988-12-27 1989-12-19 Harris Corporation Memory with cache register interface structure
GB2232797B (en) * 1989-06-16 1993-12-08 Samsung Semiconductor Inc RAM based serial memory with pipelined look-ahead reading
US4954987A (en) * 1989-07-17 1990-09-04 Advanced Micro Devices, Inc. Interleaved sensing system for FIFO and burst-mode memories
US5036493A (en) * 1990-03-15 1991-07-30 Digital Equipment Corporation System and method for reducing power usage by multiple memory modules
US5012408A (en) * 1990-03-15 1991-04-30 Digital Equipment Corporation Memory array addressing system for computer systems with multiple memory arrays
US5255242A (en) * 1990-12-17 1993-10-19 Texas Instruments Incorporated Sequential memory

Also Published As

Publication number Publication date
EP0495217A2 (en) 1992-07-22
KR100275182B1 (ko) 2000-12-15
TW198116B (OSRAM) 1993-01-11
KR920013452A (ko) 1992-07-29
JPH06131154A (ja) 1994-05-13
EP0495217A3 (en) 1992-08-12
DE69126514D1 (de) 1997-07-17
US5594700A (en) 1997-01-14
EP0495217B1 (en) 1997-06-11

Similar Documents

Publication Publication Date Title
DE3686436T2 (de) Speichersystem mit hoher leistung.
DE69230366T2 (de) Multiport statischer Direktzugriffspeicher mit schnellem Schreibdurchschema
DE69535672T2 (de) Synchrone NAND DRAM Architektur
DE2803989C2 (de) Digitaldatenspeicher mit wahlfreiem Zugriff
DE3588247T2 (de) Dynamischer Halbleiterspeicher mit einer statischen Datenspeicherzelle
DE3543911C2 (OSRAM)
DE4141892C2 (de) Halbleiterspeichereinrichtung und Verfahren zum Speichern von Daten in einer Halbleiterspeichereinrichtung
DE69132284T2 (de) Halbleiterspeicheranordnung
DE68918469T2 (de) Serieller Lesezugriff von seriellen Speichern mit einer durch den Benutzer definierten Startadresse.
DE2703578C2 (de) Videodatenspeicher
DE69326493T2 (de) Zugriffsverfahren für eine synchrone Halbleiterspeicheranordnung
DE69217761T2 (de) Lese- und Schreibschaltung für einen Speicher
DE4222273C2 (de) Zweikanalspeicher und Verfahren zur Datenübertragung in einem solchen
DE68922975T2 (de) Speichereinheit mit zwei Toren.
DE3742514C2 (OSRAM)
DE69126514T2 (de) Serieller Speicher
DE69330819T2 (de) Synchrone LSI-Speicheranordnung
DE4210857A1 (de) Halbleiterspeichereinrichtung und verfahren zum uebertragen von daten
DE19941196A1 (de) Zweikanal-FIFO mit synchronisierten Lese- und Schreibzeigern
DE19748502A1 (de) Halbleiterspeichereinrichtung, auf die mit hoher Geschwindigkeit zugegriffen werden kann
DE2828698A1 (de) Monolithischer baustein
DE4019135A1 (de) Serieller speicher auf ram-basis mit parallelem voraus-lesen
DE19653114C2 (de) Synchron-Halbleiterspeichervorrichtung, bei der ein Burstzähler gemeinsam für ein Datenschreiben und für ein Datenlesen verwendet wird
DE3786358T2 (de) Halbleiterspeicher mit System zum seriellen Schnellzugriff.
EP0393436B1 (de) Statischer Speicher mit Pipelineregistern

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee