TW198116B - - Google Patents

Info

Publication number
TW198116B
TW198116B TW081103183A TW81103183A TW198116B TW 198116 B TW198116 B TW 198116B TW 081103183 A TW081103183 A TW 081103183A TW 81103183 A TW81103183 A TW 81103183A TW 198116 B TW198116 B TW 198116B
Authority
TW
Taiwan
Application number
TW081103183A
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW198116B publication Critical patent/TW198116B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Information Transfer Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
TW081103183A 1990-12-17 1992-04-23 TW198116B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US62827990A 1990-12-17 1990-12-17

Publications (1)

Publication Number Publication Date
TW198116B true TW198116B (zh) 1993-01-11

Family

ID=24518214

Family Applications (1)

Application Number Title Priority Date Filing Date
TW081103183A TW198116B (zh) 1990-12-17 1992-04-23

Country Status (6)

Country Link
US (1) US5594700A (zh)
EP (1) EP0495217B1 (zh)
JP (1) JPH06131154A (zh)
KR (1) KR100275182B1 (zh)
DE (1) DE69126514T2 (zh)
TW (1) TW198116B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305281A (en) * 1992-08-06 1994-04-19 National Semiconductor Corporation Multiple array memory device with staggered read/write for high speed data access
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US5748539A (en) * 1997-03-05 1998-05-05 Sun Microsystems, Inc. Recursive multi-channel interface
US5933385A (en) * 1997-07-31 1999-08-03 Integrated Silicon Solution Inc. System and method for a flexible memory controller
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US6038185A (en) * 1998-05-12 2000-03-14 Atmel Corporation Method and apparatus for a serial access memory
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
JP4081963B2 (ja) * 2000-06-30 2008-04-30 セイコーエプソン株式会社 記憶装置および記憶装置に対するアクセス方法
AU2001290528A1 (en) * 2000-08-10 2002-02-18 Baxa Corporation Method, system, and apparatus for handling, labeling, filling, and capping syringes
US7392638B2 (en) * 2000-08-10 2008-07-01 Baxa Corporation Method, system, and apparatus for handling, labeling, filling, and capping syringes with improved cap
US6745277B1 (en) * 2000-10-04 2004-06-01 Force10 Networks, Inc. Intelligent interleaving scheme for multibank memory
US6430099B1 (en) 2001-05-11 2002-08-06 Broadcom Corporation Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation
KR100452640B1 (ko) * 2002-11-11 2004-10-14 한국전자통신연구원 데이터 패킷 수신 장치 및 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862419A (en) * 1983-11-10 1989-08-29 Advanced Micro Devices, Inc. High speed pointer based first-in-first-out memory
US4864543A (en) * 1987-04-30 1989-09-05 Texas Instruments Incorporated First-in, first-out memory with counter address pointers for generating multiple memory status flags
EP0272869B1 (en) * 1986-12-19 1993-07-14 Fujitsu Limited Dual port type semiconductor memory device realizing a high speed read operation
JPH0817029B2 (ja) * 1986-12-19 1996-02-21 富士通株式会社 半導体記憶装置
JP2764908B2 (ja) * 1988-02-04 1998-06-11 日本電気株式会社 カスケード・バッファ回路
JP2805761B2 (ja) * 1988-08-29 1998-09-30 日本電気株式会社 スタティックメモリ
US5027326A (en) * 1988-11-10 1991-06-25 Dallas Semiconductor Corporation Self-timed sequential access multiport memory
US4888741A (en) * 1988-12-27 1989-12-19 Harris Corporation Memory with cache register interface structure
GB2232797B (en) * 1989-06-16 1993-12-08 Samsung Semiconductor Inc RAM based serial memory with pipelined look-ahead reading
US4954987A (en) * 1989-07-17 1990-09-04 Advanced Micro Devices, Inc. Interleaved sensing system for FIFO and burst-mode memories
US5012408A (en) * 1990-03-15 1991-04-30 Digital Equipment Corporation Memory array addressing system for computer systems with multiple memory arrays
US5036493A (en) * 1990-03-15 1991-07-30 Digital Equipment Corporation System and method for reducing power usage by multiple memory modules
US5255242A (en) * 1990-12-17 1993-10-19 Texas Instruments Incorporated Sequential memory

Also Published As

Publication number Publication date
KR920013452A (ko) 1992-07-29
EP0495217B1 (en) 1997-06-11
EP0495217A3 (en) 1992-08-12
DE69126514D1 (de) 1997-07-17
EP0495217A2 (en) 1992-07-22
KR100275182B1 (ko) 2000-12-15
US5594700A (en) 1997-01-14
DE69126514T2 (de) 1997-12-04
JPH06131154A (ja) 1994-05-13

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