DE3786539T2 - Halbleiterspeicher mit Doppelzugriffseinrichtung zur Realisierung eines Lesebetriebs mit hoher Geschwindigkeit. - Google Patents

Halbleiterspeicher mit Doppelzugriffseinrichtung zur Realisierung eines Lesebetriebs mit hoher Geschwindigkeit.

Info

Publication number
DE3786539T2
DE3786539T2 DE87311041T DE3786539T DE3786539T2 DE 3786539 T2 DE3786539 T2 DE 3786539T2 DE 87311041 T DE87311041 T DE 87311041T DE 3786539 T DE3786539 T DE 3786539T DE 3786539 T2 DE3786539 T2 DE 3786539T2
Authority
DE
Germany
Prior art keywords
realizing
high speed
semiconductor memory
access device
reading operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87311041T
Other languages
English (en)
Other versions
DE3786539D1 (de
Inventor
Keizo Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP61301602A external-priority patent/JPH0817029B2/ja
Priority claimed from JP61301604A external-priority patent/JPS63155498A/ja
Priority claimed from JP61301603A external-priority patent/JPH0817030B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3786539D1 publication Critical patent/DE3786539D1/de
Publication of DE3786539T2 publication Critical patent/DE3786539T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
DE87311041T 1986-12-19 1987-12-15 Halbleiterspeicher mit Doppelzugriffseinrichtung zur Realisierung eines Lesebetriebs mit hoher Geschwindigkeit. Expired - Fee Related DE3786539T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP61301602A JPH0817029B2 (ja) 1986-12-19 1986-12-19 半導体記憶装置
JP61301604A JPS63155498A (ja) 1986-12-19 1986-12-19 半導体記憶装置
JP61301603A JPH0817030B2 (ja) 1986-12-19 1986-12-19 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3786539D1 DE3786539D1 (de) 1993-08-19
DE3786539T2 true DE3786539T2 (de) 1993-10-28

Family

ID=27338470

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87311041T Expired - Fee Related DE3786539T2 (de) 1986-12-19 1987-12-15 Halbleiterspeicher mit Doppelzugriffseinrichtung zur Realisierung eines Lesebetriebs mit hoher Geschwindigkeit.

Country Status (4)

Country Link
US (1) US4823321A (de)
EP (1) EP0272869B1 (de)
KR (1) KR910009404B1 (de)
DE (1) DE3786539T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0642196B2 (ja) * 1988-06-09 1994-06-01 株式会社東芝 倍密度走査用ラインメモリ
JP2683919B2 (ja) * 1988-07-29 1997-12-03 三菱電機株式会社 半導体記憶装置
JPH02168496A (ja) * 1988-09-14 1990-06-28 Kawasaki Steel Corp 半導体メモリ回路
US5293611A (en) * 1988-09-20 1994-03-08 Hitachi, Ltd. Digital signal processor utilizing a multiply-and-add function for digital filter realization
US5267191A (en) * 1989-04-03 1993-11-30 Ncr Corporation FIFO memory system
GB2232797B (en) * 1989-06-16 1993-12-08 Samsung Semiconductor Inc RAM based serial memory with pipelined look-ahead reading
US4967398A (en) * 1989-08-09 1990-10-30 Ford Motor Company Read/write random access memory with data prefetch
US5283763A (en) * 1989-09-21 1994-02-01 Ncr Corporation Memory control system and method
US4975601A (en) * 1989-09-29 1990-12-04 Sgs-Thomson Microelectronics, Inc. User-writable random access memory logic block for programmable logic devices
US5249154A (en) * 1989-11-28 1993-09-28 Texas Instruments Incorporated Data access controller and method
US5235543A (en) * 1989-12-29 1993-08-10 Intel Corporation Dual port static memory with one cycle read-modify-write
GB2239541B (en) * 1989-12-29 1994-05-18 Intel Corp Dual port static memory with one cycle read-modify-write operation
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US5255242A (en) * 1990-12-17 1993-10-19 Texas Instruments Incorporated Sequential memory
KR100275182B1 (ko) * 1990-12-17 2000-12-15 윌리엄 비. 켐플러 순차 메모리
JPH04257048A (ja) * 1991-02-12 1992-09-11 Mitsubishi Electric Corp デュアルポートメモリ
JP2999845B2 (ja) * 1991-04-25 2000-01-17 沖電気工業株式会社 シリアルアクセスメモリの倍速コントロール方式
JPH05266654A (ja) * 1992-03-17 1993-10-15 Mitsubishi Electric Corp マルチポートメモリ装置
US5388074A (en) * 1992-12-17 1995-02-07 Vlsi Technology, Inc. FIFO memory using single output register
US5699530A (en) * 1995-10-03 1997-12-16 Intel Corporation Circular RAM-based first-in/first-out buffer employing interleaved storage locations and cross pointers
US6286076B1 (en) * 1999-01-05 2001-09-04 Sun Microsystems, Inc. High speed memory-based buffer and system and method for use thereof
US6546461B1 (en) 2000-11-22 2003-04-08 Integrated Device Technology, Inc. Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein
AU2002235260A1 (en) * 2000-12-20 2002-07-01 Primarion, Inc. Pll/dll dual loop data synchronization utilizing a granular fifo fill level indicator
AU2002251700A1 (en) * 2000-12-20 2002-07-30 Primarion, Inc. Pll/dll dual loop data synchronization
KR20020052669A (ko) * 2000-12-26 2002-07-04 윤종용 선입 선출 메모리 및 이 메모리의 플래그 신호 발생방법
US6556495B2 (en) * 2001-07-09 2003-04-29 International Business Machines Corporation 2-D FIFO memory having full-width read/write capability
US7042792B2 (en) * 2004-01-14 2006-05-09 Integrated Device Technology, Inc. Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5255446A (en) * 1975-10-31 1977-05-06 Toshiba Corp Information transfer control system
JPS6057090B2 (ja) * 1980-09-19 1985-12-13 株式会社日立製作所 データ記憶装置およびそれを用いた処理装置
US4507760A (en) * 1982-08-13 1985-03-26 At&T Bell Laboratories First-in, first-out (FIFO) memory configuration for queue storage

Also Published As

Publication number Publication date
US4823321A (en) 1989-04-18
EP0272869A3 (en) 1990-05-23
DE3786539D1 (de) 1993-08-19
EP0272869A2 (de) 1988-06-29
KR880008324A (ko) 1988-08-30
EP0272869B1 (de) 1993-07-14
KR910009404B1 (en) 1991-11-15

Similar Documents

Publication Publication Date Title
DE3786539T2 (de) Halbleiterspeicher mit Doppelzugriffseinrichtung zur Realisierung eines Lesebetriebs mit hoher Geschwindigkeit.
DE69114881D1 (de) Analysevorrichtung zur Rettung von Halbleiterspeicherfehlern.
DE69013250D1 (de) Leseanordnung für eine Halbleiterspeicheranordnung.
DE3482511D1 (de) Adressumsetzungsgeraet fuer eine datenverarbeitungsanordnung mit virtuellem speicher.
NL191814B (nl) Halfgeleidergeheugeninrichting.
DE3684429D1 (de) Halbleiterspeicheranordnung mit einem nurlesespeicherelement zum speichern von bestimmter information.
DE3889097T2 (de) Halbleiterspeicheranordnung.
DE68923505D1 (de) Halbleiterspeicheranordnung.
DE3578989D1 (de) Halbleiterspeichergeraet mit schreibepruefoperation.
DE3883865T2 (de) Halbleiterspeicheranordnung mit einem Register.
DE68918367D1 (de) Halbleiterspeicheranordnung.
DE68905240D1 (de) Halbleiterspeichereinrichtung mit hochgeschwindigkeits-lesevorrichtung.
DE69022475T2 (de) Halbleiterspeichereinrichtung mit hoher Datenlesegeschwindigkeit.
DE68921900D1 (de) Halbleiterspeicheranordnung mit serieller Zugriffsanordnung.
DE3783569D1 (de) Halbleiterspeicher zur ausfuehrung einer selbstauffrischungsoperation.
DE68923588D1 (de) Halbleiterspeicheranordnung.
DE69022644T2 (de) Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung.
DE68909960D1 (de) Speicherschaltung mit einer Anordnung zum verbesserten seriellen Zugriff.
DE3786358D1 (de) Halbleiterspeicher mit system zum seriellen schnellzugriff.
DE3782103D1 (de) Dynamischer halbleiterspeicher mit leseschema.
DE68924080T2 (de) Halbleiterspeichervorrichtung.
DE3763267D1 (de) Datenleseschaltung fuer eine halbleiter-speichervorrichtung.
DE3784600T2 (de) Halbleiterspeicher mit schreibfunktion.
DE3767022D1 (de) Leseverstaerker fuer eine halbleiter-speicheranordnung.
DE69023556D1 (de) Halbleiterspeicher mit einem verbesserten Datenleseschema.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee