DE69125584D1 - Eine dünne Supraleiterschicht und ein Verfahren zu deren Herstellung - Google Patents

Eine dünne Supraleiterschicht und ein Verfahren zu deren Herstellung

Info

Publication number
DE69125584D1
DE69125584D1 DE69125584T DE69125584T DE69125584D1 DE 69125584 D1 DE69125584 D1 DE 69125584D1 DE 69125584 T DE69125584 T DE 69125584T DE 69125584 T DE69125584 T DE 69125584T DE 69125584 D1 DE69125584 D1 DE 69125584D1
Authority
DE
Germany
Prior art keywords
production
superconductor layer
thin superconductor
thin
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69125584T
Other languages
English (en)
Other versions
DE69125584T3 (de
DE69125584T2 (de
Inventor
Keizo Harada
Hidenori Nakanishi
Hideo Itozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=18519600&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69125584(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Application granted granted Critical
Publication of DE69125584D1 publication Critical patent/DE69125584D1/de
Publication of DE69125584T2 publication Critical patent/DE69125584T2/de
Publication of DE69125584T3 publication Critical patent/DE69125584T3/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming copper oxide superconductor layers
    • H10N60/0576—Processes for depositing or forming copper oxide superconductor layers characterised by the substrate
    • H10N60/0632—Intermediate layers, e.g. for growth control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/922—Static electricity metal bleed-off metallic stock
    • Y10S428/9265—Special properties
    • Y10S428/93—Electric superconducting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/70—High TC, above 30 k, superconducting device, article, or structured stock
    • Y10S505/701—Coated or thin film device, i.e. active or passive

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
DE69125584T 1990-12-13 1991-12-13 Eine dünne Supraleiterschicht und ein Verfahren zu deren Herstellung Expired - Fee Related DE69125584T3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2410432A JPH04214097A (ja) 1990-12-13 1990-12-13 超電導薄膜の作製方法

Publications (3)

Publication Number Publication Date
DE69125584D1 true DE69125584D1 (de) 1997-05-15
DE69125584T2 DE69125584T2 (de) 1997-11-13
DE69125584T3 DE69125584T3 (de) 2002-07-11

Family

ID=18519600

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69125584T Expired - Fee Related DE69125584T3 (de) 1990-12-13 1991-12-13 Eine dünne Supraleiterschicht und ein Verfahren zu deren Herstellung

Country Status (4)

Country Link
US (1) US5416062A (de)
EP (1) EP0490776B2 (de)
JP (1) JPH04214097A (de)
DE (1) DE69125584T3 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69219816T2 (de) * 1991-03-11 1997-10-23 Sumitomo Electric Industries Supraleitende Dünnschicht mit mindestens einer isolierten Region, gebildet aus oxydisch supraleitendem Material und Verfahren zu ihrer Herstellung
JPH04300292A (ja) * 1991-03-26 1992-10-23 Sumitomo Electric Ind Ltd 複合酸化物超電導薄膜の成膜方法
JPH04342497A (ja) * 1991-05-20 1992-11-27 Sumitomo Electric Ind Ltd 複合酸化物超電導薄膜の成膜方法
EP0973208B1 (de) * 1992-07-28 2005-04-27 Nippon Telegraph And Telephone Corporation Vorrichtung mit Gitteranpassung und Verfahren zu ihrer Herstellung
FR2726399B1 (fr) * 1994-10-27 1997-01-10 Alsthom Cge Alcatel Procede pour la preparation d'un substrat en vue du depot d'une couche mince de materiau supraconducteur
US6517944B1 (en) 2000-08-03 2003-02-11 Teracomm Research Inc. Multi-layer passivation barrier for a superconducting element
JP4457587B2 (ja) 2002-09-05 2010-04-28 セイコーエプソン株式会社 電子デバイス用基体の製造方法及び電子デバイスの製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8901874A (nl) * 1989-07-20 1991-02-18 Philips Nv Planaire josephson inrichting.
US5122509A (en) * 1990-04-30 1992-06-16 Advanced Technology Materials, Inc. High temperature superconductor/diamond composite article, and method of making the same

Also Published As

Publication number Publication date
US5416062A (en) 1995-05-16
DE69125584T3 (de) 2002-07-11
DE69125584T2 (de) 1997-11-13
JPH04214097A (ja) 1992-08-05
EP0490776B2 (de) 2001-10-31
EP0490776A3 (en) 1992-11-19
EP0490776B1 (de) 1997-04-09
EP0490776A2 (de) 1992-06-17

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8366 Restricted maintained after opposition proceedings
8339 Ceased/non-payment of the annual fee