DE69124972D1 - Gate-Array mit eingebauter Programmierungsschaltung - Google Patents

Gate-Array mit eingebauter Programmierungsschaltung

Info

Publication number
DE69124972D1
DE69124972D1 DE69124972T DE69124972T DE69124972D1 DE 69124972 D1 DE69124972 D1 DE 69124972D1 DE 69124972 T DE69124972 T DE 69124972T DE 69124972 T DE69124972 T DE 69124972T DE 69124972 D1 DE69124972 D1 DE 69124972D1
Authority
DE
Germany
Prior art keywords
built
gate array
programming circuit
programming
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69124972T
Other languages
English (en)
Other versions
DE69124972T2 (de
Inventor
Kueing-Long Chen
David Kuan-Yu Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69124972D1 publication Critical patent/DE69124972D1/de
Application granted granted Critical
Publication of DE69124972T2 publication Critical patent/DE69124972T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Read Only Memory (AREA)
DE69124972T 1991-01-02 1991-12-19 Gate-Array mit eingebauter Programmierungsschaltung Expired - Fee Related DE69124972T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/636,818 US5166557A (en) 1991-01-02 1991-01-02 Gate array with built-in programming circuitry

Publications (2)

Publication Number Publication Date
DE69124972D1 true DE69124972D1 (de) 1997-04-10
DE69124972T2 DE69124972T2 (de) 1997-06-12

Family

ID=24553453

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69124972T Expired - Fee Related DE69124972T2 (de) 1991-01-02 1991-12-19 Gate-Array mit eingebauter Programmierungsschaltung

Country Status (5)

Country Link
US (1) US5166557A (de)
EP (1) EP0493937B1 (de)
JP (1) JPH04317223A (de)
KR (1) KR100214195B1 (de)
DE (1) DE69124972T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367208A (en) 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US5302546A (en) * 1991-07-31 1994-04-12 Quicklogic Corporation Programming of antifuses
US5412261A (en) * 1992-04-14 1995-05-02 Aptix Corporation Two-stage programmable interconnect architecture
JP2909328B2 (ja) * 1992-11-02 1999-06-23 株式会社東芝 フィールドプログラマブルゲートアレイ
US5524243A (en) * 1992-12-16 1996-06-04 Rolm Company Parallel programming of field programmable gate array devices
JPH06318864A (ja) * 1993-05-07 1994-11-15 Toshiba Corp フィールドプログラマブルゲートアレイ
US5412593A (en) * 1994-01-12 1995-05-02 Texas Instruments Incorporated Fuse and antifuse reprogrammable link for integrated circuits
US5537056A (en) * 1994-09-30 1996-07-16 Actel Corporation Antifuse-based FPGA architecture without high-voltage isolation transistors
US5751162A (en) * 1995-04-06 1998-05-12 Texas Instruments Incorporated Field programmable gate array logic module configurable as combinational or sequential circuits
US5959466A (en) 1997-01-31 1999-09-28 Actel Corporation Field programmable gate array with mask programmed input and output buffers
US6150837A (en) * 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US5811870A (en) 1997-05-02 1998-09-22 International Business Machines Corporation Antifuse structure
US7248094B1 (en) * 2004-11-24 2007-07-24 Actel Corporation Circuit and method for supplying programming potential at voltages larger than BVDss of programming transistors

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6048106B2 (ja) * 1979-12-24 1985-10-25 富士通株式会社 半導体集積回路
US4785199A (en) * 1983-11-28 1988-11-15 Stanford University Programmable complementary transistors
JPS6134967A (ja) * 1984-05-03 1986-02-19 デイジタル　イクイプメント　コ−ポレ−シヨン Ｖｌｓｉ集積回路装置用の入力保護構成体
US4703206A (en) * 1985-11-19 1987-10-27 Signetics Corporation Field-programmable logic device with programmable foldback to control number of logic levels
US4859874A (en) * 1987-09-25 1989-08-22 Fairchild Semiconductor Corp. PLA driver with reconfigurable drive
US4990802A (en) * 1988-11-22 1991-02-05 At&T Bell Laboratories ESD protection for output buffers

Also Published As

Publication number Publication date
EP0493937A3 (en) 1993-02-24
KR920015733A (ko) 1992-08-27
EP0493937A2 (de) 1992-07-08
KR100214195B1 (ko) 1999-08-02
EP0493937B1 (de) 1997-03-05
JPH04317223A (ja) 1992-11-09
US5166557A (en) 1992-11-24
DE69124972T2 (de) 1997-06-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee