DE69124582D1 - Verfahren zur Dickenkontrolle eines dünnen einkristallinen Filmes auf einem SOI Substrat - Google Patents
Verfahren zur Dickenkontrolle eines dünnen einkristallinen Filmes auf einem SOI SubstratInfo
- Publication number
- DE69124582D1 DE69124582D1 DE69124582T DE69124582T DE69124582D1 DE 69124582 D1 DE69124582 D1 DE 69124582D1 DE 69124582 T DE69124582 T DE 69124582T DE 69124582 T DE69124582 T DE 69124582T DE 69124582 D1 DE69124582 D1 DE 69124582D1
- Authority
- DE
- Germany
- Prior art keywords
- thickness
- controlling
- soi substrate
- crystalline film
- thin single
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B11/00—Measuring arrangements characterised by the use of optical techniques
- G01B11/02—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness
- G01B11/06—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness for measuring thickness ; e.g. of sheet material
- G01B11/0616—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness for measuring thickness ; e.g. of sheet material of coating
- G01B11/0683—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness for measuring thickness ; e.g. of sheet material of coating measurement during deposition or removal of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Metallurgy (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Organic Chemistry (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Plasma & Fusion (AREA)
- Recrystallisation Techniques (AREA)
- Drying Of Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2332867A JPH0834198B2 (ja) | 1990-11-28 | 1990-11-28 | Soi基板における単結晶薄膜層の膜厚制御方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69124582D1 true DE69124582D1 (de) | 1997-03-20 |
DE69124582T2 DE69124582T2 (de) | 1997-09-04 |
Family
ID=18259691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69124582T Expired - Fee Related DE69124582T2 (de) | 1990-11-28 | 1991-11-26 | Verfahren zur Dickenkontrolle eines dünnen einkristallinen Filmes auf einem SOI Substrat |
Country Status (4)
Country | Link |
---|---|
US (1) | US5223080A (de) |
EP (1) | EP0488642B1 (de) |
JP (1) | JPH0834198B2 (de) |
DE (1) | DE69124582T2 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5643472A (en) * | 1988-07-08 | 1997-07-01 | Cauldron Limited Partnership | Selective removal of material by irradiation |
JPH0817166B2 (ja) * | 1991-04-27 | 1996-02-21 | 信越半導体株式会社 | 超薄膜soi基板の製造方法及び製造装置 |
US5254830A (en) * | 1991-05-07 | 1993-10-19 | Hughes Aircraft Company | System for removing material from semiconductor wafers using a contained plasma |
EP0547677A3 (en) * | 1991-12-17 | 1996-10-16 | Philips Nv | Use of vapor-phase etching in fabrication of semiconductor-on-insulator structure |
US5282921A (en) * | 1992-06-16 | 1994-02-01 | Hughes Aircraft Company | Apparatus and method for optimally scanning a two-dimensional surface of one or more objects |
JPH06140365A (ja) * | 1992-10-23 | 1994-05-20 | Shin Etsu Handotai Co Ltd | Soi基板におけるsoi膜厚均一化方法 |
US5360509A (en) * | 1993-03-08 | 1994-11-01 | Gi Corporation | Low cost method of fabricating epitaxial semiconductor devices |
JP3313840B2 (ja) | 1993-09-14 | 2002-08-12 | 富士通株式会社 | 半導体装置の製造方法 |
US5419803A (en) * | 1993-11-17 | 1995-05-30 | Hughes Aircraft Company | Method of planarizing microstructures |
IL112511A0 (en) * | 1994-02-18 | 1995-05-26 | Hughes Aircraft Co | System for improving the total thickness variation of a wafer |
US5571429A (en) * | 1994-02-25 | 1996-11-05 | Litel Instruments | Apparatus and process for high speed laminate processing with computer generated holograms |
US5937312A (en) * | 1995-03-23 | 1999-08-10 | Sibond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator wafers |
US5494849A (en) * | 1995-03-23 | 1996-02-27 | Si Bond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator substrates |
US5635414A (en) * | 1995-03-28 | 1997-06-03 | Zakaluk; Gregory | Low cost method of fabricating shallow junction, Schottky semiconductor devices |
US5795493A (en) * | 1995-05-01 | 1998-08-18 | Motorola, Inc. | Laser assisted plasma chemical etching method |
JPH10233375A (ja) * | 1997-02-19 | 1998-09-02 | Sony Corp | 被加工物の表面加工方法及び半導体薄層の形成方法 |
US6014944A (en) * | 1997-09-19 | 2000-01-18 | The United States Of America As Represented By The Secretary Of The Navy | Apparatus for improving crystalline thin films with a contoured beam pulsed laser |
US6248651B1 (en) | 1998-06-24 | 2001-06-19 | General Semiconductor, Inc. | Low cost method of fabricating transient voltage suppressor semiconductor devices or the like |
TW580581B (en) * | 1998-11-10 | 2004-03-21 | Mosel Vitelic Inc | Method of estimating thin-film thickness and formation conditions |
JP2000173976A (ja) * | 1998-12-02 | 2000-06-23 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US6096579A (en) * | 1999-03-25 | 2000-08-01 | Vanguard International Semiconductor Corporation | Method for controlling the thickness of a passivation layer on a semiconductor device |
US6380367B1 (en) | 1999-11-18 | 2002-04-30 | Basf Corporation | Continuous process for the production of sucrose based polyether polyols |
JP3893868B2 (ja) * | 2000-10-11 | 2007-03-14 | 東京エレクトロン株式会社 | 電界効果トランジスタの製造方法、並びに、半導体デバイスの製造方法及びその装置 |
DE102004054566B4 (de) | 2004-11-11 | 2008-04-30 | Siltronic Ag | Verfahren und Vorrichtung zum Einebnen einer Halbleiterscheibe sowie Halbleiterscheibe mit verbesserter Ebenheit |
DE102006022093B4 (de) * | 2006-05-11 | 2010-04-08 | Siltronic Ag | Verfahren und Vorrichtung zur Behandlung einer Halbleiterscheibe durch Ätzen |
KR100810633B1 (ko) * | 2006-05-17 | 2008-03-06 | 삼성에스디아이 주식회사 | 레이저 조사장치, 레이저 결정화 장치 및 그를 이용한결정화 방법 |
DE102006023497B4 (de) | 2006-05-18 | 2008-05-29 | Siltronic Ag | Verfahren zur Behandlung einer Halbleiterscheibe |
DE102007006151B4 (de) | 2007-02-07 | 2008-11-06 | Siltronic Ag | Verfahren zur Verringerung und Homogenisierung der Dicke einer Halbleiterschicht, die sich auf der Oberfläche eines elektrisch isolierenden Materials befindet |
KR101484296B1 (ko) * | 2007-06-26 | 2015-01-19 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 기판의 제작방법 |
US8163628B2 (en) * | 2007-11-01 | 2012-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor substrate |
FR3002687B1 (fr) * | 2013-02-26 | 2015-03-06 | Soitec Silicon On Insulator | Procede de traitement d une structure |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4367044A (en) * | 1980-12-31 | 1983-01-04 | International Business Machines Corp. | Situ rate and depth monitor for silicon etching |
JPS62245636A (ja) * | 1986-04-18 | 1987-10-26 | Hitachi Ltd | 観察装置 |
JPH0669085B2 (ja) * | 1986-09-05 | 1994-08-31 | 富士通株式会社 | 半導体基板の製造方法 |
US4717446A (en) * | 1986-09-18 | 1988-01-05 | Motorola Inc. | Method of detecting the endpoint of the etch of epitaxially grown silicon |
JPH02196425A (ja) * | 1989-01-25 | 1990-08-03 | Tokai Univ | 紫外レーザー光によるエッチング方法 |
US5131752A (en) * | 1990-06-28 | 1992-07-21 | Tamarack Scientific Co., Inc. | Method for film thickness endpoint control |
JPH0475337A (ja) * | 1990-07-17 | 1992-03-10 | Seiko Epson Corp | 半導体基板の研磨法 |
-
1990
- 1990-11-28 JP JP2332867A patent/JPH0834198B2/ja not_active Expired - Lifetime
-
1991
- 1991-11-26 DE DE69124582T patent/DE69124582T2/de not_active Expired - Fee Related
- 1991-11-26 EP EP91310868A patent/EP0488642B1/de not_active Expired - Lifetime
- 1991-11-27 US US07/799,182 patent/US5223080A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69124582T2 (de) | 1997-09-04 |
EP0488642A3 (de) | 1994-02-23 |
JPH04196559A (ja) | 1992-07-16 |
US5223080A (en) | 1993-06-29 |
JPH0834198B2 (ja) | 1996-03-29 |
EP0488642A2 (de) | 1992-06-03 |
EP0488642B1 (de) | 1997-02-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |