DE69225881T2 - Verfahren zur Herstellung eines Substrates vom SOI-Typ mit einer uniformen dünnen Silizium-Schicht - Google Patents

Verfahren zur Herstellung eines Substrates vom SOI-Typ mit einer uniformen dünnen Silizium-Schicht

Info

Publication number
DE69225881T2
DE69225881T2 DE69225881T DE69225881T DE69225881T2 DE 69225881 T2 DE69225881 T2 DE 69225881T2 DE 69225881 T DE69225881 T DE 69225881T DE 69225881 T DE69225881 T DE 69225881T DE 69225881 T2 DE69225881 T2 DE 69225881T2
Authority
DE
Germany
Prior art keywords
producing
silicon layer
type substrate
thin silicon
uniform thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69225881T
Other languages
English (en)
Other versions
DE69225881D1 (de
Inventor
Takao Abe
Masatake Katayama
Akio Kanai
Konomu Ohki
Masatake Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Application granted granted Critical
Publication of DE69225881D1 publication Critical patent/DE69225881D1/de
Publication of DE69225881T2 publication Critical patent/DE69225881T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/127—Process induced defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
DE69225881T 1991-12-27 1992-02-25 Verfahren zur Herstellung eines Substrates vom SOI-Typ mit einer uniformen dünnen Silizium-Schicht Expired - Fee Related DE69225881T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3358935A JP2602597B2 (ja) 1991-12-27 1991-12-27 薄膜ｓｏｉ基板の製造方法

Publications (2)

Publication Number Publication Date
DE69225881D1 DE69225881D1 (de) 1998-07-16
DE69225881T2 true DE69225881T2 (de) 1998-10-15

Family

ID=18461881

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69225881T Expired - Fee Related DE69225881T2 (de) 1991-12-27 1992-02-25 Verfahren zur Herstellung eines Substrates vom SOI-Typ mit einer uniformen dünnen Silizium-Schicht

Country Status (4)

Country Link
US (1) US5240883A (de)
EP (1) EP0554498B1 (de)
JP (1) JP2602597B2 (de)
DE (1) DE69225881T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3192000B2 (ja) * 1992-08-25 2001-07-23 キヤノン株式会社 半導体基板及びその作製方法
US5360509A (en) * 1993-03-08 1994-11-01 Gi Corporation Low cost method of fabricating epitaxial semiconductor devices
US5346848A (en) * 1993-06-01 1994-09-13 Motorola, Inc. Method of bonding silicon and III-V semiconductor materials
JP2833519B2 (ja) * 1994-09-27 1998-12-09 日本電気株式会社 絶縁膜上の半導体膜の薄膜化方法および薄膜化装置
US5455193A (en) * 1994-11-17 1995-10-03 Philips Electronics North America Corporation Method of forming a silicon-on-insulator (SOI) material having a high degree of thickness uniformity
US5635414A (en) * 1995-03-28 1997-06-03 Zakaluk; Gregory Low cost method of fabricating shallow junction, Schottky semiconductor devices
US5674758A (en) * 1995-06-06 1997-10-07 Regents Of The University Of California Silicon on insulator achieved using electrochemical etching
US5869386A (en) * 1995-09-28 1999-02-09 Nec Corporation Method of fabricating a composite silicon-on-insulator substrate
US6383849B1 (en) * 1996-06-29 2002-05-07 Hyundai Electronics Industries Co., Ltd. Semiconductor device and method for fabricating the same
US6248651B1 (en) 1998-06-24 2001-06-19 General Semiconductor, Inc. Low cost method of fabricating transient voltage suppressor semiconductor devices or the like
US6482725B1 (en) 1999-08-18 2002-11-19 Advanced Micro Devices, Inc. Gate formation method for reduced poly-depletion and boron penetration
US7358586B2 (en) * 2004-09-28 2008-04-15 International Business Machines Corporation Silicon-on-insulator wafer having reentrant shape dielectric trenches
US7211474B2 (en) * 2005-01-18 2007-05-01 International Business Machines Corporation SOI device with body contact self-aligned to gate
JP2009076694A (ja) * 2007-09-20 2009-04-09 Panasonic Corp 窒化物半導体装置およびその製造方法
US9393669B2 (en) * 2011-10-21 2016-07-19 Strasbaugh Systems and methods of processing substrates
US9457446B2 (en) 2012-10-01 2016-10-04 Strasbaugh Methods and systems for use in grind shape control adaptation
US9610669B2 (en) 2012-10-01 2017-04-04 Strasbaugh Methods and systems for use in grind spindle alignment
CN104505403A (zh) * 2015-01-28 2015-04-08 桂林电子科技大学 一种具有介质层固定电荷的soi功率器件
US10134837B1 (en) 2017-06-30 2018-11-20 Qualcomm Incorporated Porous silicon post processing

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4649627A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation Method of fabricating silicon-on-insulator transistors with a shared element
NL8501773A (nl) * 1985-06-20 1987-01-16 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen.
US4601779A (en) * 1985-06-24 1986-07-22 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
JPH01186612A (ja) * 1988-01-14 1989-07-26 Fujitsu Ltd 半導体基板の製造方法
EP0378906A1 (de) * 1988-12-08 1990-07-25 Fujitsu Limited Verfahren zur Herstellung einer Halbleiter-auf-Isolator-Struktur und Halbleiterbauelement, das die Halbleiter-auf-Isolator-Struktur enthält
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer

Also Published As

Publication number Publication date
EP0554498A2 (de) 1993-08-11
US5240883A (en) 1993-08-31
DE69225881D1 (de) 1998-07-16
JP2602597B2 (ja) 1997-04-23
EP0554498B1 (de) 1998-06-10
JPH05182881A (ja) 1993-07-23
EP0554498A3 (de) 1994-03-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee