DE69031326T2 - Treiberkreis - Google Patents
TreiberkreisInfo
- Publication number
- DE69031326T2 DE69031326T2 DE69031326T DE69031326T DE69031326T2 DE 69031326 T2 DE69031326 T2 DE 69031326T2 DE 69031326 T DE69031326 T DE 69031326T DE 69031326 T DE69031326 T DE 69031326T DE 69031326 T2 DE69031326 T2 DE 69031326T2
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- output
- mos transistor
- voltage
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000003990 capacitor Substances 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 10
- 101100195396 Human cytomegalovirus (strain Merlin) RL11 gene Proteins 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000007667 floating Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1158757A JP3066595B2 (ja) | 1989-06-20 | 1989-06-20 | 駆動回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69031326D1 DE69031326D1 (de) | 1997-10-02 |
| DE69031326T2 true DE69031326T2 (de) | 1998-01-02 |
Family
ID=15678679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69031326T Expired - Fee Related DE69031326T2 (de) | 1989-06-20 | 1990-06-18 | Treiberkreis |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0405812B1 (enExample) |
| JP (1) | JP3066595B2 (enExample) |
| KR (1) | KR0184636B1 (enExample) |
| DE (1) | DE69031326T2 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07111084A (ja) * | 1993-10-13 | 1995-04-25 | Oki Micro Design Miyazaki:Kk | 半導体集積回路装置 |
| JP2842181B2 (ja) * | 1993-11-04 | 1998-12-24 | 日本電気株式会社 | 半導体メモリ装置 |
| US5534797A (en) * | 1994-12-23 | 1996-07-09 | At&T Corp. | Compact and fast row driver/decoder for semiconductor memory |
| JP5034233B2 (ja) * | 2005-12-28 | 2012-09-26 | 富士通株式会社 | アドレスデコーダ，記憶装置，処理装置及び記憶装置におけるアドレスデコード方法 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60253091A (ja) * | 1984-05-30 | 1985-12-13 | Fujitsu Ltd | 半導体記憶装置 |
| JPS62232796A (ja) * | 1986-04-01 | 1987-10-13 | Toshiba Corp | 半導体記憶装置 |
| US4769784A (en) * | 1986-08-19 | 1988-09-06 | Advanced Micro Devices, Inc. | Capacitor-plate bias generator for CMOS DRAM memories |
-
1989
- 1989-06-20 JP JP1158757A patent/JP3066595B2/ja not_active Expired - Lifetime
-
1990
- 1990-06-18 DE DE69031326T patent/DE69031326T2/de not_active Expired - Fee Related
- 1990-06-18 EP EP90306608A patent/EP0405812B1/en not_active Expired - Lifetime
- 1990-06-19 KR KR1019900008999A patent/KR0184636B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0405812A3 (enExample) | 1994-04-06 |
| JPH0323592A (ja) | 1991-01-31 |
| EP0405812A2 (en) | 1991-01-02 |
| KR0184636B1 (ko) | 1999-04-15 |
| KR910001770A (ko) | 1991-01-31 |
| JP3066595B2 (ja) | 2000-07-17 |
| DE69031326D1 (de) | 1997-10-02 |
| EP0405812B1 (en) | 1997-08-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |