DE69017319D1 - E2PROM mit in einem Halbleitersubstrat geformten schwebenden Gate und Herstellungsverfahren. - Google Patents
E2PROM mit in einem Halbleitersubstrat geformten schwebenden Gate und Herstellungsverfahren.Info
- Publication number
- DE69017319D1 DE69017319D1 DE69017319T DE69017319T DE69017319D1 DE 69017319 D1 DE69017319 D1 DE 69017319D1 DE 69017319 T DE69017319 T DE 69017319T DE 69017319 T DE69017319 T DE 69017319T DE 69017319 D1 DE69017319 D1 DE 69017319D1
- Authority
- DE
- Germany
- Prior art keywords
- e2prom
- manufacturing
- semiconductor substrate
- floating gate
- gate molded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1230110A JPH0393276A (ja) | 1989-09-05 | 1989-09-05 | 半導体記憶装置及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69017319D1 true DE69017319D1 (de) | 1995-04-06 |
| DE69017319T2 DE69017319T2 (de) | 1995-08-03 |
Family
ID=16902721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69017319T Expired - Fee Related DE69017319T2 (de) | 1989-09-05 | 1990-09-05 | E2PROM mit in einem Halbleitersubstrat geformten schwebenden Gate und Herstellungsverfahren. |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0416574B1 (de) |
| JP (1) | JPH0393276A (de) |
| KR (1) | KR930010250B1 (de) |
| DE (1) | DE69017319T2 (de) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3124334B2 (ja) * | 1991-10-03 | 2001-01-15 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
| US5355330A (en) * | 1991-08-29 | 1994-10-11 | Hitachi, Ltd. | Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode |
| US5622881A (en) * | 1994-10-06 | 1997-04-22 | International Business Machines Corporation | Packing density for flash memories |
| US5818082A (en) * | 1996-03-04 | 1998-10-06 | Advanced Micro Devices, Inc. | E2 PROM device having erase gate in oxide isolation region in shallow trench and method of manufacture thereof |
| DE10054172C2 (de) * | 2000-11-02 | 2002-12-05 | Infineon Technologies Ag | Halbleiter-Speicherzelle mit einer in einem Graben angeordneten Floating-Gate-Elektrode und Verfahren zu deren Herstellung |
| KR20180007411A (ko) | 2016-07-13 | 2018-01-23 | 두산인프라코어 주식회사 | 엔진 배기 브레이크를 이용한 엑슬 과열 방지 시스템 및 방법 |
| WO2018111299A1 (en) * | 2016-12-16 | 2018-06-21 | Kimberly-Clark Worldwide, Inc. | Wet-laid microfibers including polyolefin and thermoplastic starch |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59154071A (ja) * | 1983-02-23 | 1984-09-03 | Toshiba Corp | 半導体装置 |
| JPS59172270A (ja) * | 1983-03-18 | 1984-09-28 | Toshiba Corp | 半導体装置及びその製造方法 |
| JPS61294869A (ja) * | 1985-06-21 | 1986-12-25 | Toshiba Corp | 半導体装置およびその製造方法 |
| JPS6288368A (ja) * | 1985-10-15 | 1987-04-22 | Seiko Instr & Electronics Ltd | 半導体不揮発性メモリ |
| US4796228A (en) * | 1986-06-02 | 1989-01-03 | Texas Instruments Incorporated | Erasable electrically programmable read only memory cell using trench edge tunnelling |
| JPH01143362A (ja) * | 1987-11-30 | 1989-06-05 | Sony Corp | 不揮発性メモリ装置 |
-
1989
- 1989-09-05 JP JP1230110A patent/JPH0393276A/ja active Pending
-
1990
- 1990-09-05 DE DE69017319T patent/DE69017319T2/de not_active Expired - Fee Related
- 1990-09-05 EP EP90117064A patent/EP0416574B1/de not_active Expired - Lifetime
- 1990-09-05 KR KR1019900013983A patent/KR930010250B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0416574A3 (en) | 1991-04-10 |
| JPH0393276A (ja) | 1991-04-18 |
| DE69017319T2 (de) | 1995-08-03 |
| KR930010250B1 (ko) | 1993-10-15 |
| EP0416574A2 (de) | 1991-03-13 |
| KR910007139A (ko) | 1991-04-30 |
| EP0416574B1 (de) | 1995-03-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |