DE68924495T2 - Halbleiter-Bauelement mit verbesserter Gate-Kapazität und dessen Herstellungsverfahren. - Google Patents

Halbleiter-Bauelement mit verbesserter Gate-Kapazität und dessen Herstellungsverfahren.

Info

Publication number
DE68924495T2
DE68924495T2 DE68924495T DE68924495T DE68924495T2 DE 68924495 T2 DE68924495 T2 DE 68924495T2 DE 68924495 T DE68924495 T DE 68924495T DE 68924495 T DE68924495 T DE 68924495T DE 68924495 T2 DE68924495 T2 DE 68924495T2
Authority
DE
Germany
Prior art keywords
manufacturing process
semiconductor component
gate capacitance
improved gate
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68924495T
Other languages
English (en)
Other versions
DE68924495D1 (de
Inventor
Nobuyasu Kitaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE68924495D1 publication Critical patent/DE68924495D1/de
Application granted granted Critical
Publication of DE68924495T2 publication Critical patent/DE68924495T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE68924495T 1988-04-25 1989-04-25 Halbleiter-Bauelement mit verbesserter Gate-Kapazität und dessen Herstellungsverfahren. Expired - Lifetime DE68924495T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63101811A JPH0752774B2 (ja) 1988-04-25 1988-04-25 半導体装置

Publications (2)

Publication Number Publication Date
DE68924495D1 DE68924495D1 (de) 1995-11-16
DE68924495T2 true DE68924495T2 (de) 1996-04-25

Family

ID=14310516

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68924495T Expired - Lifetime DE68924495T2 (de) 1988-04-25 1989-04-25 Halbleiter-Bauelement mit verbesserter Gate-Kapazität und dessen Herstellungsverfahren.

Country Status (3)

Country Link
EP (1) EP0339586B1 (de)
JP (1) JPH0752774B2 (de)
DE (1) DE68924495T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130266A (en) * 1990-08-28 1992-07-14 United Microelectronics Corporation Polycide gate MOSFET process for integrated circuits
JP2951082B2 (ja) * 1991-10-24 1999-09-20 株式会社東芝 半導体記憶装置およびその製造方法
JP3236720B2 (ja) * 1993-02-10 2001-12-10 三菱電機株式会社 半導体記憶装置およびその製造方法
US6057604A (en) * 1993-12-17 2000-05-02 Stmicroelectronics, Inc. Integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure
JP3123937B2 (ja) * 1996-11-26 2001-01-15 日本電気株式会社 半導体装置およびその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128670A (en) * 1977-11-11 1978-12-05 International Business Machines Corporation Fabrication method for integrated circuits with polysilicon lines having low sheet resistance
DE2943150A1 (de) * 1978-10-25 1980-05-08 Hitachi Ltd Verfahren zur herstellung einer halbleitervorrichtung
GB2077993A (en) * 1980-06-06 1981-12-23 Standard Microsyst Smc Low sheet resistivity composite conductor gate MOS device
DE3131875A1 (de) * 1980-08-18 1982-03-25 Fairchild Camera and Instrument Corp., 94042 Mountain View, Calif. "verfahren zum herstellen einer halbleiterstruktur und halbleiterstruktur"
JPS61136274A (ja) * 1984-12-07 1986-06-24 Toshiba Corp 半導体装置
JPS61150376A (ja) * 1984-12-25 1986-07-09 Toshiba Corp 半導体装置
JPS61224459A (ja) * 1985-03-29 1986-10-06 Toshiba Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP0339586B1 (de) 1995-10-11
JPH0752774B2 (ja) 1995-06-05
EP0339586A3 (en) 1990-10-10
DE68924495D1 (de) 1995-11-16
EP0339586A2 (de) 1989-11-02
JPH01273347A (ja) 1989-11-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP